{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:18:46Z","timestamp":1725488326900},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540649496"},{"type":"electronic","value":"9783540680611"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1998]]},"DOI":"10.1007\/3-540-68061-6_33","type":"book-chapter","created":{"date-parts":[[2007,8,7]],"date-time":"2007-08-07T06:02:15Z","timestamp":1186466535000},"page":"360-364","source":"Crossref","is-referenced-by-count":0,"title":["A Reconfigurable Hardware Tool for High Speed Network Simulation"],"prefix":"10.1007","author":[{"given":"Cyril","family":"Labb\u00e9","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fr\u00e9d\u00e9ric","family":"Reblewski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Serge","family":"Martin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Marc","family":"Vincent","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2000,3,16]]},"reference":[{"key":"33_CR1","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1016\/0166-5316(92)90014-8","volume":"14","author":"A. Gravey","year":"1992","unstructured":"A. Gravey and G. H\u00e9buterne. Simultaneity in discrete-time single server queues with Bernouilli inputs. Performance Evaluation North-Holland, 14:123\u2013131, 1992.","journal-title":"Performance Evaluation North-Holland"},{"key":"33_CR2","unstructured":"C. Labb\u00e9, F. Reblewski, and J-M Vincent. Performance evaluation of high speed network protocols by emulation on a versatile architecture. RAIRO, Syst\u00e8mes \u00e0 \u00e9v\u00e9nements discrets stochastiques: th\u00e9orie, application et outils., to be published."},{"key":"33_CR3","first-page":"51","volume":"30","author":"J. Pellaumail","year":"1996","unstructured":"J. Pellaumail. Majoration des retards dans les r\u00e9seaux ATM. Rairo recherche op\u00e9rationnelle, 30:51\u201364, 1996.","journal-title":"Rairo recherche op\u00e9rationnelle"},{"key":"33_CR4","doi-asserted-by":"crossref","unstructured":"L. Burgun, F. Reblewski, G. Fenelon, J. Barbier, and O. Lepape. Serial fault emulation. In Proceedings of the 33rd Design Automation Conference 1996 (DAC 96), pages 801\u2013806, Metasystems, France, 1996.","DOI":"10.1109\/DAC.1996.545681"},{"key":"33_CR5","doi-asserted-by":"crossref","unstructured":"R. Airiau, J.-M. Berge, and V. Olive. Circuit Synthesis with VHDL. Kluwer Academic Publishers, France Telecom, 1994.","DOI":"10.1007\/978-1-4615-2760-2"},{"key":"33_CR6","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-61815-5","volume-title":"Can self-similar traffic be modeled by markovian processes?","author":"S. Robert","year":"1996","unstructured":"S. Robert and J.-Y. Le Boudec. Can self-similar traffic be modeled by markovian processes? Lecture Notes in Computer Science, 1044, 1996."},{"key":"33_CR7","series-title":"Lect Notes Comput Sci","first-page":"1567","volume-title":"Survey of ATM switch architectures","author":"R.Y. Awdeh","year":"1995","unstructured":"R.Y. Awdeh and H.T. Mouftah. Survey of ATM switch architectures. Lecture Notes in Computer Science, 27:1567\u20131613, 1995."},{"key":"33_CR8","doi-asserted-by":"crossref","unstructured":"D. Stiliadis and A. Varma. A reconfigurable hardware approach to network simulation. ACM Transaction on Modeling and Computer Simulation, 7, 1997.","DOI":"10.1145\/244804.244809"},{"key":"33_CR9","unstructured":"L. Truffet. M\u00e9thodes de Calcul de Bornes Stochastiques sur des Mod\u00e8les de Syst\u00e8mes et de R\u00e9seaux. PhD thesis, Universit\u00e9 Paris VI, 1995."}],"container-title":["Lecture Notes in Computer Science","Computer Performance Evaluation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-68061-6_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T20:07:52Z","timestamp":1556741272000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-68061-6_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998]]},"ISBN":["9783540649496","9783540680611"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/3-540-68061-6_33","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[1998]]}}}