{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T18:34:26Z","timestamp":1725474866089},"reference-count":13,"publisher":"Springer US","isbn-type":[{"type":"print","value":"9780387346328"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-0-387-34733-2_11","type":"book-chapter","created":{"date-parts":[[2006,11,27]],"date-time":"2006-11-27T12:41:06Z","timestamp":1164631266000},"page":"107-113","source":"Crossref","is-referenced-by-count":2,"title":["Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs"],"prefix":"10.1007","author":[{"given":"Abdelmajid","family":"Bouajila","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Bernauer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Herkersdorf","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wolfgang","family":"Rosenstiel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Bringmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Walter","family":"Stechele","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"4","key":"11_CR1","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/2.585154","volume":"30","author":"A. Avizienis","year":"1997","unstructured":"A. Avizienis, Toward Systematic Design of Fault-Tolerant Systems, IEEE Computer 30(4), 51\u201358 (1997).","journal-title":"IEEE Computer"},{"key":"11_CR2","doi-asserted-by":"crossref","unstructured":"G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann and W. Stechele, Towards a Framework and a Design Methodology for Autonomic SoC, in: 2nd ICAC (2005).","DOI":"10.1109\/ICAC.2005.61"},{"key":"11_CR3","doi-asserted-by":"crossref","unstructured":"A. Avizienis, J.-C. Laprie, B. Randell and C. Landwehr, Basic Concepts and Taxonomy of Dependable and Secure Computing, IEEE Trans. on Dependable and Secure Computing 1(1) (2004).","DOI":"10.1109\/TDSC.2004.2"},{"issue":"7","key":"11_CR4","doi-asserted-by":"crossref","first-page":"783","DOI":"10.1109\/43.644041","volume":"16","author":"N. Touba","year":"1997","unstructured":"N. Touba and E. McCluskey, Logic Synthesis of Multilevel Circuits with Concurrent Error Detection, IEEE Trans. CAD 16(7), 783\u2013789 (1997).","journal-title":"IEEE Trans. CAD"},{"key":"11_CR5","doi-asserted-by":"crossref","unstructured":"M. Nicolaidis, Efficient Implementations of Self-Checking Adders and ALUs, in: Proc. 23rd Intl. Symp. Fault-Tolerant Computing, pp. 586\u2013595 (1993).","DOI":"10.1109\/FTCS.1993.627361"},{"key":"11_CR6","doi-asserted-by":"crossref","unstructured":"D. Ernst, N. S. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T. Mudge and K. Flautner, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, in: Proc. 36th Intl. Symp. Microarch., pp. 7\u201318 (2003).","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"11_CR7","doi-asserted-by":"crossref","unstructured":"M. Nicolaidis, Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies, in: Proc. 17th IEEE VLSI Test Symposium, pp. 86\u201394 (1999).","DOI":"10.1109\/VTEST.1999.766651"},{"issue":"2","key":"11_CR8","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1109\/MC.2005.70","volume":"38","author":"S. Mitra","year":"2005","unstructured":"S. Mitra, N. Seifert, M. Zhang, Q. Shi and K. S. Kim, Robust System Design with Built-in Soft-Error Resilience, IEEE Computer 38(2), 43\u201352 (2005).","journal-title":"IEEE Computer"},{"key":"11_CR9","doi-asserted-by":"crossref","unstructured":"L. Anghel and M. Nicolaidis, Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, in: Proc. DATE, pp. 591\u2013598 (2000).","DOI":"10.1145\/343647.343863"},{"key":"11_CR10","first-page":"1","volume":"2","author":"T._.M. Austin","year":"2000","unstructured":"T._M. Austin, DIVA: A Dynamic Approach to Microprocessor Design, Journal of Instruction-Level Parallelism 2, 1\u20136 (2000).","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"11_CR11","doi-asserted-by":"crossref","unstructured":"C. Weaver and T. Austin, A Fault Tolerant Approach to Microprocessor Design, in: Proc. Intl. Conf. Dependable Systems and Networks, pp. 411\u2013420 (2001).","DOI":"10.1109\/DSN.2001.941425"},{"issue":"2","key":"11_CR12","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1162\/evco.1995.3.2.149","volume":"3","author":"S. W. Wilson","year":"1995","unstructured":"S. W. Wilson, Classifier Fitness Based on Accuracy, Evolutionary Computation 3(2), 149\u2013175 (1995).","journal-title":"Evolutionary Computation"},{"key":"11_CR13","unstructured":"LEON VHDL code is available at www.gaisler.com."}],"container-title":["IFIP International Federation for Information Processing","Biologically Inspired Cooperative Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-0-387-34733-2_11.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,28]],"date-time":"2021-04-28T01:50:15Z","timestamp":1619574615000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-0-387-34733-2_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9780387346328"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-0-387-34733-2_11","relation":{},"subject":[]}}