{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,11,10]],"date-time":"2026-11-10T21:05:26Z","timestamp":1794344726657,"version":"4.9.0"},"publisher-location":"Boston, MA","reference-count":27,"publisher":"Springer US","isbn-type":[{"value":"9780387393612","type":"print"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-0-387-39362-9_1","type":"book-chapter","created":{"date-parts":[[2007,1,28]],"date-time":"2007-01-28T00:17:58Z","timestamp":1169943478000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Design Challenges in Multiprocessor Systems-on-Chip"],"prefix":"10.1007","author":[{"given":"Wayne","family":"Wolf","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","reference":[{"issue":"2\u20133","key":"1_CR1","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","volume":"50","author":"E. Bolotin","year":"2004","unstructured":"E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, \u201cQNoC: QoS architecture and design process for network on chip,\u201d The Journal of Systems Architecture, 50(2\u20133), February 2004, pp. 105\u2013128.","journal-title":"The Journal of Systems Architecture"},{"key":"1_CR2","doi-asserted-by":"crossref","unstructured":"Francky Catthoor, Sven Wuytack, Eddy De Greef, Florin Balasa, Lode Nachtergaele, and Arnout Vandecappelle, Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design, Norwell MA: Kluwer Academic Publishers, 1998.","DOI":"10.1007\/978-1-4757-2849-1"},{"key":"1_CR3","unstructured":"Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis,Giuseppe Maruccia, and Francesco Papariello, \u201cOCCN\u201d a network-on-chip modeling and simulation framework,\u201d inProceedings of the Conference on Design Automation and Test in Europe, vol. 3, IEEE Computer Society Press, 2004, p. 30174."},{"issue":"10","key":"1_CR4","first-page":"900","volume":"17","author":"D. P. Bharat","year":"1998","unstructured":"Bharat P. Dave and Niraj K. Jha, \u201cCOHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems,\u201d IEEE Transactions on CAD\/ICAS, 17(10), October 1998, pp.900\u2013919.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"issue":"1","key":"1_CR5","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1109\/92.748204","volume":"7","author":"D. P. Bharat","year":"1999","unstructured":"Bharat P. Dave, Ganesh Lakshminarayana, and Niraj K. Jha, \u201cCOSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems,\u201d IEEE Transactions on VLSI Systems, 7(1), March 1999, pp.92\u2013104.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"1_CR6","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1023\/A:1008857008151","volume":"2","author":"P. Eles","year":"1996","unstructured":"Petru Eles, Zebo Peng, Krzysztof Kuchcinski, and Alexa Doboli, \u201cSystem level hardware\/software partitioning based on simulated annealing and tabu search,\u201d Design Automation for Embedded Systems, 2,1996, pp. 5\u201332.","journal-title":"Design Automation for Embedded Systems"},{"issue":"4","key":"1_CR7","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1109\/54.245964","volume":"10","author":"R. Ernst","year":"1993","unstructured":"Rolf Ernst, Joerg Henkel,and Thomas Benner, \u201cHardware-software cosynthesis for microcontrollers,\u201d IEEE Design and Test of Computers,10(4), December 1993, pp. 64\u201375.","journal-title":"IEEE Design and Test of Computers"},{"key":"1_CR8","unstructured":"G. Goossens, \u201cApplication-specific networks-on-chips,\u201d inA. Jerraya and W. Wolf, eds., Multiprocessor Systems-on-Chips, Morgan Kaufman, 2004."},{"key":"1_CR9","doi-asserted-by":"crossref","unstructured":"Pierre Guerrier and Alain Greiner, \u201cA generic architecture for on-chip packet-switched interconnections,\u201d inProceedings of the Conference on Design Automation and Test in Europe, ACM Press, 2000, pp. 250\u2013256.","DOI":"10.1145\/343647.343776"},{"issue":"3","key":"1_CR10","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1109\/54.232470","volume":"10","author":"K. Rajesh","year":"1993","unstructured":"Rajesh K. Gupta and Giovanni De Micheli, \u201cHardware-software cosynthesis for digital systems,\u201d IEEE Design and Test of Computers, 10(3), September 1993, pp. 29\u201340.","journal-title":"IEEE Design and Test of Computers"},{"issue":"11","key":"1_CR11","first-page":"1138","volume":"20","author":"A. Hoffman","year":"2001","unstructured":"Andreas Hoffman, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, and Heinrich Meyr, \u201cA novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language,\u201d IEEE Transactions on CAD\/ICAS, 20(11), November 2001, pp. 1138\u20131354.","journal-title":"IEEE Transactions on CAD\/ICAS"},{"key":"1_CR12","doi-asserted-by":"crossref","unstructured":"Wen-Mei W. Hwu and Pohua P. Chang, \u201cAchieving high instruction cache performance with an optimizing compiler,\u201d inProceedings of the 16th Annual International Symposium on Computer Architecture, ACM,1989, pp. 242\u2013251.","DOI":"10.1145\/74926.74953"},{"key":"1_CR13","doi-asserted-by":"crossref","unstructured":"Makiko Itoh, Shigeaki Higaki, Jun Sato, Akichika Shiomi, Yoshinori Takuchi, Akira Kitajima, and Masaharu Imai, \u201cPEAS-III: an ASIP design environment,\u201d inInternational Conference on Computer Design: VLSI in Computers and Processors, IEEE Computer Society Press, 2000, pp. 430\u2013436.","DOI":"10.1109\/ICCD.2000.878319"},{"key":"1_CR14","doi-asserted-by":"crossref","unstructured":"A. Jalabert, S. Murali, L. Benini, and G. De Micheli, \u201cxpipesCompiler: a tool for instantiating application specific networks-on-chips,\u201d inProceedings of Design Automation and Testing in Europe Conference,IEEE, 2004, pp. 884\u2013889.","DOI":"10.1109\/DATE.2004.1268999"},{"key":"1_CR15","unstructured":"Sashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Mikael Millberg, Jonny Oberg, Kari Tiensyrja, and Ahmed Hemani, \u201cA network on chip architecture and design methodology,\u201d inProceedings of the IEEE Computer Society Annual Symposium on VLSI, IEEE Computer Society Press, 2002."},{"issue":"5","key":"1_CR16","doi-asserted-by":"publisher","first-page":"422","DOI":"10.1109\/MDT.2005.103","volume":"22","author":"S.-J. Lee","year":"2005","unstructured":"Se-Joong Lee, Kangmin Lee, and Hoi-Jun Yoo, \u201cAnalysis and implementation of practical, cost-effective networks-on-chips,\u201d IEEE Design & Test of Computers, 22(5), September\/October 2005, pp. 422\u2013433.","journal-title":"IEEE Design & Test of Computers"},{"key":"1_CR17","doi-asserted-by":"publisher","first-page":"195","DOI":"10.1023\/A:1008884219274","volume":"2","author":"J. Madsen","year":"1997","unstructured":"J. Madsen, J. Grode, P. V. Knudsen, M. E. Petersen, and A. Haxthausen, \u201cLYCOS: the Lyngby Co-Synthesis System,\u201d Design Automation for Embedded Systems, 2, 1997, pp. 195\u2013235.","journal-title":"Design Automation for Embedded Systems"},{"key":"1_CR18","doi-asserted-by":"crossref","unstructured":"Scott McFarling, \u201cProgram optimization for instruction caches,\u201dProceedings of the Third International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, 1989, pp. 183\u2013191.","DOI":"10.1145\/70082.68200"},{"key":"1_CR19","unstructured":"Object Management Group, CORBA Basics, 2006, http:\/\/www.omg.org\/gettingstarted\/corbafaq.htm."},{"key":"1_CR20","doi-asserted-by":"crossref","unstructured":"M. D. Osso, G. Biccari, L. Giovanni, D. Bertozzi, and L. Benini, \u201cxpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs,\u201d in Proceedings of the 21 st International Conference on Computer Design, IEEE Computer Society Press, 2003, pp. 536\u2013539.","DOI":"10.1109\/ICCD.2003.1240952"},{"issue":"4","key":"1_CR21","doi-asserted-by":"publisher","first-page":"384","DOI":"10.1145\/268424.268464","volume":"2","author":"P. R. Panda","year":"1997","unstructured":"Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau, \u201cMemory data organization for improved cache performance in embedded processor applications,\u201d ACM Transactions on Design Automation of Electronic Systems, 2(4), October 1997, pp. 384\u2013409.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"3","key":"1_CR22","doi-asserted-by":"publisher","first-page":"682","DOI":"10.1145\/348019.348570","volume":"5","author":"P. R. Panda","year":"2000","unstructured":"Preeti Ranjan Panda, Nikil D. Dutt, and Alexandru Nicolau, \u201cOn-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems,\u201d ACM Transactions on Design Automation of Embedded Systems, 5(3), July 2000, pp. 682\u2013704.","journal-title":"ACM Transactions on Design Automation of Embedded Systems"},{"key":"1_CR23","unstructured":"Toshiyuki Sasaki, Shinsuke Kobayashi, Tomohide Maeda, Makkiko Itoh, Yoshinori Takeushi, and Masahiru Imai, \u201cRapid prototyping of complex instructions for embedded processors using PEAS-III,\u201d inProceedings, SASIMI 2001, October, 2001, pp. 61\u201366."},{"issue":"6","key":"1_CR24","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/2.846319","volume":"33","author":"D. C","year":"2000","unstructured":"Douglas C. Schmidt and Fred Kuhns, \u201cAn overview of the real-time CORBA specification,\u201d IEEE Computer, 33(6), June 2000, pp. 56\u201363.","journal-title":"IEEE Computer"},{"key":"1_CR25","doi-asserted-by":"crossref","unstructured":"S. Vercauteren, B. Lin, and H. De Man, \u201cA strategy for real-time kernel support in application-specific HW\/SW embedded architectures,\u201d in Proceedings, 33 rd Design Automation Conference, ACM Press, 1996,pp. 678\u2013683.","DOI":"10.1145\/240518.240646"},{"issue":"2","key":"1_CR26","doi-asserted-by":"publisher","first-page":"218","DOI":"10.1109\/92.585225","volume":"5","author":"W. Wolf","year":"1997","unstructured":"Wayne Wolf, \u201cAn architectural co-synthesis algorithm for distributed embedded computing systems,\u201d IEEE Transactions on VLSI Systems, 5(2), June 1997, pp. 218\u201329.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"1_CR27","unstructured":"Jiang Xu, Wayne Wolf, Joerg Henkel, and Srimat Chakradhar, \u201cA design methodology for application-specific networks-on-chips,\u201d ACM Transactions on Embedded Computing Systems, to appear in the Special Issue on Multiprocessor Systems-on-Chips."}],"container-title":["IFIP International Federation for Information Processing","From Model-Driven Design to Resource Management for Distributed Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-0-387-39362-9_1.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,13]],"date-time":"2025-01-13T01:49:01Z","timestamp":1736732941000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-0-387-39362-9_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9780387393612"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/978-0-387-39362-9_1","relation":{"is-part-of":[{"id-type":"doi","id":"https:\/\/doi.org\/10.1007\/978-0-387-39362-9","asserted-by":"object"}]},"subject":[]}}