{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T05:28:29Z","timestamp":1737437309797,"version":"3.33.0"},"publisher-location":"Boston, MA","reference-count":18,"publisher":"Springer US","isbn-type":[{"type":"print","value":"9780387736600"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-0-387-73661-7_17","type":"book-chapter","created":{"date-parts":[[2007,9,11]],"date-time":"2007-09-11T00:22:03Z","timestamp":1189470123000},"page":"267-281","source":"Crossref","is-referenced-by-count":12,"title":["Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles"],"prefix":"10.1007","author":[{"given":"N.","family":"Badereddine","sequence":"first","affiliation":[]},{"given":"P.","family":"Girard","sequence":"additional","affiliation":[]},{"given":"S.","family":"Pravossoudovitch","sequence":"additional","affiliation":[]},{"given":"A.","family":"Virazel","sequence":"additional","affiliation":[]},{"given":"C.","family":"Landrault","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"17_CR1_17","unstructured":"Semiconductor Industry Association (SIA), \u201cInternational Technology Roadmap for Semiconductors (ITRS)\u201d, 2005 Edition."},{"key":"17_CR2_17","unstructured":"M.L. Bushnell and V.D. Agrawal, \u201cEssentials of Electronic Testing\u201d, Kluwer Academic Publishers, 2000."},{"key":"17_CR3_17","unstructured":"C. Shi and R. Kapur, \u201cHow Power Aware Test Improves Reliability and Yield\u201d, IEEDesign.com, September 15, 2004."},{"key":"17_CR4_17","doi-asserted-by":"crossref","unstructured":"J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, N.V. Arvind, P. Sreeprakash and M. Hachinger, \u201cA Case Study of IR-Drop in Structured At-Speed Testing\u201d, IEEE International Test Conference, pp. 1098-1104, 2003.","DOI":"10.1109\/TEST.2003.1271098"},{"issue":"12","key":"17_CR5_17","doi-asserted-by":"crossref","first-page":"1325","DOI":"10.1109\/43.736572","volume":"17","author":"V. Dabholkar","year":"1998","unstructured":"V. Dabholkar, S. Chakravarty, I. Pomeranz and S.M. Reddy, \u201cTechniques for Reducing Power Dissipation During Test Application in Full Scan Circuits\u201d, IEEE Transactions on CAD, Vol. 17, N\u00b0 12, pp. 1325-1333, December 1998.","journal-title":"IEEE Transactions on CAD"},{"key":"17_CR6_17","doi-asserted-by":"crossref","unstructured":"Y. Bonhomme, P. Girard, C. Landrault and S. Pravossoudovitch, \u201cPower Driven Chaining of Flip-flops in Scan Architectures\u201d, IEEE Int'l Test Conf., pp. 796-803, 2002.","DOI":"10.1109\/TEST.2002.1041833"},{"key":"17_CR7_17","doi-asserted-by":"crossref","unstructured":"Y. Bonhomme, P. Girard, L. Guiller, C. Landrault and S. Pravossoudovitch, \u201cEfficien t Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint\u201d, IEEE Int'l Test Conf., pp. 488-493, 2003.","DOI":"10.1109\/TEST.2003.1270874"},{"issue":"3","key":"17_CR8_17","doi-asserted-by":"publisher","first-page":"82","DOI":"10.1109\/MDT.2002.1003802","volume":"19","author":"P. Girard","year":"2002","unstructured":"P. Girard, \u201cSurvey of Low-Power Testing of VLSI Circuits\u201d, IEEE Design & Test of Computers, Vol. 19, N\u00b0 3, pp. 82-92, May-June 2002.","journal-title":"IEEE Design & Test of Computers"},{"key":"17_CR9_17","unstructured":"N. Nicolici and B. Al-Hashimi, \u201cPower-Constrained Testing of VLSI Circuits\u201d, Springer Publishers, 2003."},{"key":"17_CR10_17","doi-asserted-by":"crossref","unstructured":"K.M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain and J. Lewis, \u201cMinimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques\u201d, IEEE Int'l Test Conf., pp. 355-364, 2004.","DOI":"10.1109\/TEST.2004.1386971"},{"key":"17_CR11_17","unstructured":"TetraMAX\u2122, Version 2001.08, Synopsys Inc., 2001."},{"key":"17_CR12_17","unstructured":"PowerMill\u00ae, Version 5.4, Synopsys Inc., 2000."},{"key":"17_CR13_17","doi-asserted-by":"crossref","unstructured":"R. Sankaralingam, R. Oruganti and N. Touba, \u201cStatic Compaction Techniques to Control Scan Vector Power Dissipation\u201d, IEEE VLSI Test Symp., pp. 35-42 , 2000.","DOI":"10.1109\/VTEST.2000.843824"},{"key":"17_CR14_17","unstructured":"\u201cModern Heuristic Techniques for Combinatorial Problems\u201d, Edited by C.R. Reeves, Backwell Scientific Publications, 1993."},{"issue":"4598","key":"17_CR15_17","doi-asserted-by":"publisher","first-page":"671","DOI":"10.1126\/science.220.4598.671","volume":"220","author":"S. Kirkpatrick","year":"1983","unstructured":"S. Kirkpatrick, C. D. Gelatt Jr., M. P. Vecchi, \u201cOptimization by Simulated Annealing\u201d, Science, 220, 4598, 671-680, 1983.","journal-title":"Science"},{"key":"17_CR16_17","doi-asserted-by":"crossref","unstructured":"M. Hirech, J. Beausang and X. Gu, \u201cA New Approach to Scan Chain Reordering Using Physical Design Information\u201d, IEEE Int'l Test Conf., pp. 348-355, 1998.","DOI":"10.1109\/TEST.1998.743173"},{"key":"17_CR17_17","doi-asserted-by":"crossref","unstructured":"D. Berthelot, S. Chaudhuri and H. Savoj, \u201cAn Efficient Linear-Time Algorithm for Scan Chain Optimization and Repartitioning\u201d, IEEE Int'l Test Conf., pp. 781-787, 2002.","DOI":"10.1109\/TEST.2002.1041831"},{"key":"17_CR18_17","unstructured":"\u201cSilicon Ensemble\u00ae\u201d, Cadence Design System, 2000."}],"container-title":["IFIP International Federation for Information Proc","Vlsi-Soc: From Systems To Silicon"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-0-387-73661-7_17.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T23:05:51Z","timestamp":1737414351000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-0-387-73661-7_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9780387736600"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-0-387-73661-7_17","relation":{},"subject":[]}}