{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T05:27:14Z","timestamp":1737437234706,"version":"3.33.0"},"publisher-location":"Boston, MA","reference-count":10,"publisher":"Springer US","isbn-type":[{"type":"print","value":"9780387736600"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-0-387-73661-7_2","type":"book-chapter","created":{"date-parts":[[2007,9,11]],"date-time":"2007-09-11T00:22:03Z","timestamp":1189470123000},"page":"11-24","source":"Crossref","is-referenced-by-count":2,"title":["Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals"],"prefix":"10.1007","author":[{"given":"Fraidy","family":"Bouesse","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Renaudin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gilles","family":"Sicard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"2_CR1_2","unstructured":"P. Kocher, J. Jaffe, B. Jun, \u201cDifferential Power Analysis,\u201d Advances in Cryptology -Crypto 99 Proceedings, Lecture Notes In Computer Science Vol. 1666, M. Wiener ed., Springer-Verlag, 1999."},{"key":"2_CR2_2","doi-asserted-by":"crossref","unstructured":"Simon Moore, Ross Anderson, Paul Cunningham, Robert Mullins, George Taylor, \u201cImproving Smart Card Security using Self-timed Circuits\u201d, Eighth International Symposium on Asynchronous Circuits and systems (ASYNC2002). 8-11 April 2002. Manchester, U.K.","DOI":"10.1109\/ASYNC.2002.1000311"},{"key":"2_CR3_2","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1109\/ASYNC.2002.1000310","volume-title":"Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYN 2002)","author":"L. A. Plana","year":"2002","unstructured":"L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, J. D. Garside and S. Temple, \u201cSPA -A Synthesisable Amulet Core for Smartcard Applications\u201d, Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC 2002). Pages 201-210. Manchester, 8-11\/04\/2002. Published by the IEEE Computer Society."},{"key":"2_CR4_2","first-page":"137","volume":"2779","author":"J. A Jacques","year":"2003","unstructured":"Jacques J. A Fournier, Simon Moore, Huiyun Li, Robert Mullins, and Gerorge Taylor,\u201cSecurity Evalution of Asunchronous Circuits\u201d, CHES 2003, LNCS 2779, pp 137-151, 2003.","journal-title":"CHES 2003, LNCS"},{"key":"2_CR5_2","unstructured":"F. Bouesse, M. Renaudin, B. Robisson, E Beigne, P.Y. Liardet, S. Prevosto, J. Sonzogni, \u201cDPA on Quasi Delay Insensitive Asynchronous circuits: Concrete Results\u201d, To be published in XIX Conference on Design of Circuits and Integrated Systems Bordeaux, France, November 24-26, 2004."},{"key":"2_CR6_2","doi-asserted-by":"crossref","unstructured":"G.F. Bouesse, M. Renaudin, S. Dumont, F. Germain, \u00ab DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement \u00bb, DATE 2005. p. 424","DOI":"10.1109\/DATE.2005.124"},{"key":"2_CR7_2","unstructured":"T. S. Messerges and E. A. Dabbish, R. H. Sloan, \u201cInvestigations of Power Analysis Attacks on Smartcards\u201d, USENIX Workshop on Smartcard Technology, Chicago, Illinois, USE, May 10-11, 1999."},{"key":"2_CR8_2","doi-asserted-by":"crossref","unstructured":"Marc Renaudin, \u201cAsynchronous circuits and systems: a promising designalternative\u201d, Microelectronic for Telecommunications : managing high complexity and mobility\u201d (MIGAS 2000), special issue of the Microelectronics-Engineering Journal, Elsevier Science, GUEST Editors : P; Senn, M. Renaudin, J, Boussey, Vol. 54, N\u00b0 1-2, December 2000, pp. 133-149.","DOI":"10.1016\/S0167-9317(00)80065-9"},{"key":"2_CR9_2","first-page":"415","volume-title":"Cryptographic Hardware and Embedded Systems (CHES 2002), Redwood Shore, USA, LNCS No. 2523","author":"V. Fischer","year":"2002","unstructured":"Viktor Fischer, M. Drutarovsk\u00fd, True Random Number Generator Embedded in Reconfigurable Hardware, In C. K. Ko\u00e7, and C. Paar, (Eds.): Cryptographic Hardware and Embedded Systems (CHES 2002), Redwood Shore, USA, LNCS No. 2523, Springer, Berlin, Germany, ISBN 3-540-00409-2, pp. 415-430."},{"key":"2_CR10_2","first-page":"555","volume-title":"\u201cField-Programmable Logic and Applications,\u201d 14th International Conference, FPL 2004, Antwerp, Belgium, August 30-September 1, 2004, LNCS 3203","author":"V. Fischer","year":"2004","unstructured":"V. Fischer, M. Drutarovsk\u00fd, M. \u0160imka, N. Bochard, High Performance True Random Number Generator in Altera Stratix FPLDs, in J. Becker, M. Platzner, S. Vernalde (Eds.): \u201cField-Programmable Logic and Applications,\u201d 14th International Conference, FPL 2004, Antwerp, Belgium, August 30-September 1, 2004, LNCS 3203, Springer, Berlin, Germany, pp. 555-564."}],"container-title":["IFIP International Federation for Information Proc","Vlsi-Soc: From Systems To Silicon"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-0-387-73661-7_2.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T23:05:32Z","timestamp":1737414332000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-0-387-73661-7_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9780387736600"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-0-387-73661-7_2","relation":{},"subject":[]}}