{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,23]],"date-time":"2025-01-23T05:30:22Z","timestamp":1737610222146,"version":"3.33.0"},"publisher-location":"Boston, MA","reference-count":40,"publisher":"Springer US","isbn-type":[{"type":"print","value":"9780387749082"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-0-387-74909-9_19","type":"book-chapter","created":{"date-parts":[[2007,11,21]],"date-time":"2007-11-21T02:51:41Z","timestamp":1195613501000},"page":"337-355","source":"Crossref","is-referenced-by-count":2,"title":["Designing Routing and Message-Dependent Deadlock Free Networks on Chips"],"prefix":"10.1007","author":[{"given":"Srinivasan","family":"Murali","sequence":"first","affiliation":[]},{"given":"Paolo","family":"Meloni","sequence":"additional","affiliation":[]},{"given":"Federico","family":"Angiolini","sequence":"additional","affiliation":[]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[]},{"given":"Salvatore","family":"Carta","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"Micheli","sequence":"additional","affiliation":[]},{"given":"Luigi","family":"Raffo","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"19_CR1_19","doi-asserted-by":"crossref","unstructured":"L. Benini and G. De Micheli, \u201cNetworks on Chips: A New SoC Paradigm\u201d, IEEE Computers, pp. 70-78, Jan. 2002.","DOI":"10.1109\/2.976921"},{"key":"19_CR2_19","doi-asserted-by":"crossref","unstructured":"M. Sgroi et al., \u201cAddressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design\u201d, Proc. DAC, pp. 667-672, June 2001.","DOI":"10.1145\/378239.379045"},{"key":"19_CR3_19","doi-asserted-by":"crossref","unstructured":"S. Kumar et al., \u201cA Network on Chip Architecture and Design Methodology\u201d, Proc. ISVLSI, pp. 117-122, April 2002","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"19_CR4_19","doi-asserted-by":"crossref","unstructured":"P. Guerrier, A. Greiner, \u201cA generic architecture for on-chip packet-switched inter- connections\u201d, Proc. DATE, pp. 250-256, March 2000.","DOI":"10.1145\/343647.343776"},{"issue":"5","key":"19_CR5_19","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/MDT.2005.99","volume":"22","author":"K. Goossens","year":"2005","unstructured":"K. Goossens et al., \u201cThe Aethereal network on chip: Concepts, architectures, and implementations\u201d, IEEE Design and Test of Computers, Vol. 22(5), pp. 21-31, Sept-Oct 2005.","journal-title":"IEEE Design and Test of Computers"},{"key":"19_CR6_19","doi-asserted-by":"crossref","unstructured":"W. Dally, B. Towles, \u201cRoute Packets, not Wires: On-Chip Interconnection Net-works\u201d, Proc. DAC, pp. 684-689, June 2001.","DOI":"10.1145\/378239.379048"},{"issue":"3","key":"19_CR7_19","first-page":"259","volume":"14","author":"Y. H. Song","year":"2003","unstructured":"Y. H. Song, T. M. Pinkston, \u201cA Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems\u201d, IEEE TPDS, Vol. 14(3), pp. 259-275, March 2003.","journal-title":"IEEE TPDS"},{"key":"19_CR8_19","unstructured":"Y. Choi, \u201cDeadlock Recovery Based Router Architectures for High Performance Networks\u201d, PhD Dissertation, University of Southern California, June 2001."},{"issue":"7","key":"19_CR9_19","first-page":"729","volume":"11","author":"G. Chiu","year":"2000","unstructured":"G. Chiu, \u201cThe Odd-Even Turn Model for Adaptive Routing\u201d, IEEE TPDS, Vol. 11 (7), pp. 729-738, July 2000.","journal-title":"IEEE TPDS"},{"key":"19_CR10_19","doi-asserted-by":"crossref","unstructured":"C. Glass, L. Ni, \u201cThe turn model for adaptive routing\u201d, Proc. ISCA, pp. 278-287, 1992.","DOI":"10.1145\/146628.140384"},{"issue":"8","key":"19_CR11_19","first-page":"790","volume":"8","author":"J. Duato","year":"1997","unstructured":"J. Duato, \u201cA New Theory of Deadlock-Free Adaptive Routing in Wormhole Net-works\u201d, IEEE TPDS, Vol. 8(8), pp. 790-802, Aug 1997.","journal-title":"IEEE TPDS"},{"issue":"3","key":"19_CR12_19","doi-asserted-by":"publisher","first-page":"411","DOI":"10.1109\/TNET.2003.813040","volume":"11","author":"D. Starobinksi","year":"2003","unstructured":"D. Starobinksi et al., \u201cApplication of network calculus to general topologies using turn-prohibition\u201d, IEEE\/ACM Transactions on Networking, Vol. 11, Issue 3, pp. 411-421, June 2003.","journal-title":"IEEE\/ACM Transactions on Networking"},{"issue":"4","key":"19_CR13_19","first-page":"466","volume":"4","author":"W. J. Dally","year":"1993","unstructured":"W. J. Dally, H. Aoki, \u201cDeadlock-Free Adaptive Routing in Multi-computer Net-works Using Virtual Channels\u201d, IEEE TPDS, Vol. 4(4), pp. 466-475, April 1993.","journal-title":"IEEE TPDS"},{"key":"19_CR14_19","doi-asserted-by":"crossref","unstructured":"S. Scott, G. Thorson, Optimized Routing in the Cray T3D\u201d, Proc. Workshop Parallel Computer Routing and Comm., pp. 281-294, May 1994.","DOI":"10.1007\/3-540-58429-3_44"},{"key":"19_CR15_19","first-page":"147","volume":"IV","author":"S. Scott","year":"1996","unstructured":"S. Scott, G. Thorson, \u201cThe Cray T3E Network: Adaptive Routing in a High Per-formance 3D Torus\u201d, Proc. Symp. Hot Interconnects IV, pp. 147-156, Aug. 1996.","journal-title":"Proc. Symp. Hot Interconnects"},{"key":"19_CR16_19","first-page":"157","volume":"IV","author":"J. Carbonaro","year":"1996","unstructured":"J. Carbonaro, Cavallino, \u201cThe Teraflops Router and NIC\u201d, Proc. Symp. Hot In-terconnects IV, pp. 157-160, Aug. 1996.","journal-title":"Symp. Hot In-terconnects"},{"key":"19_CR17_19","doi-asserted-by":"publisher","first-page":"113","DOI":"10.1109\/HIS.2001.946702","volume":"9","author":"S.S. Mukherjee","year":"2001","unstructured":"S.S. Mukherjee et al., \u201cThe Alpha 21364 Network Architecture\u201d, Proc. Symp. HOT Interconnects 9, pp. 113-117, Aug. 2001.","journal-title":"Proc. Symp. HOT Interconnects"},{"key":"19_CR18_19","unstructured":"L. Widdoes, S. Correll, :The S-1 Project: Developing High Performance Comput-ers\u201d, Proc. COMPCON, pp. 282-291, Spring 1980."},{"key":"19_CR19_19","unstructured":"\u201c http:\/\/www.st.com\u201d ."},{"key":"19_CR20_19","doi-asserted-by":"crossref","unstructured":"J. Laudon, D. Lenoski,\u201d The SGI Origin: A ccNUMA Highly Scalable Server\u201d, Proc. ISCA, pp. 241-251, June 1997.","DOI":"10.1145\/264107.264206"},{"key":"19_CR21_19","doi-asserted-by":"crossref","unstructured":"D. Lenoski et al., \u201c The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor\u201d, Proc. ISCA, pp. 148-159, 1990.","DOI":"10.1145\/325096.325132"},{"key":"19_CR22_19","unstructured":"A. Hansson, K. Goossens, A. Radulescu, \u201cUMARS: A Unified Approach to Map-ping and Routing on a Combined Guaranteed Service and Best-Effort Network-on-Chip Architecture\u201d, Technical Report 2005\/00340, Philips Research, April 2005."},{"key":"19_CR23_19","doi-asserted-by":"crossref","unstructured":"B. Gebremichael et al., \u201cDeadlock Prevention in the Aethereal Protocol\u201d, Proc. Working Conference on Correct Hardware Design and Verification Methods (CHARME), Oct 2005.","DOI":"10.1007\/11560548_28"},{"key":"19_CR24_19","unstructured":"J. Hu, R. Marculescu, \u2019Exploiting the Routing Flexibility for Energy\/Performance Aware Mapping of Regular NoC Architectures\u2019, Proc. DATE, March 2003."},{"key":"19_CR25_19","doi-asserted-by":"crossref","unstructured":"S. Murali, G. De Micheli, \u201cSUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs\u201d, Proc. DAC 2004.","DOI":"10.1145\/996566.996809"},{"key":"19_CR26_19","doi-asserted-by":"crossref","unstructured":"S. Murali et al., \u201cMapping and Physical Planning of Networks on Chip Architec-tures with Quality-of-Service Guarantees\u201d, Proc. ASPDAC 2005.","DOI":"10.1145\/1120725.1120737"},{"key":"19_CR27_19","doi-asserted-by":"crossref","unstructured":"A.Pinto et al., \u201cEfficient Synthesis of Networks on Chip\u201d, ICCD 2003, pp. 146-150, Oct 2003.","DOI":"10.1109\/ICCD.2003.1240887"},{"key":"19_CR28_19","unstructured":"W.H.Ho, T.M.Pinkston, \u201cA Methodology for Designing Efficient On-Chip Inter-connects on Well-Behaved Communication Patterns\u201d, HPCA 2003, pp. 377-388, Feb 2003."},{"key":"19_CR29_19","doi-asserted-by":"crossref","unstructured":"T. Ahonen et al. \u201dTopology Optimization for Application Specific Networks on Chip\u201d, Proc. SLIP 04.","DOI":"10.1145\/966747.966758"},{"key":"19_CR30_19","doi-asserted-by":"crossref","unstructured":"K. Srinivasan et al., \u201cAn Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection Networks\u201d, Proc. ICCAD \u201905.","DOI":"10.1109\/ICCAD.2005.1560070"},{"key":"19_CR31_19","doi-asserted-by":"crossref","unstructured":"A. Hansson et al., \u201cA unified approach to constrained mapping and routing on network-on-chip architectures\u201d, pp. 75-80, Proc. ISSS 2005.","DOI":"10.1145\/1084834.1084857"},{"key":"19_CR32_19","doi-asserted-by":"crossref","unstructured":"S. Murali et al., \u201cDesigning Application-Specific Networks on Chips using Floor-plan Information\u201d, Proc. ICCAD 2006.","DOI":"10.1109\/ICCAD.2006.320058"},{"key":"19_CR33_19","unstructured":"W. J. Dally, B. Towles, \u201dPrinciples and Practices of Interconnection Networks\u201d, Morgan Kaufmann , Dec 2003."},{"key":"19_CR34_19","unstructured":"\u201c http:\/\/www.synopsys.com \u201d."},{"key":"19_CR35_19","unstructured":"\u201c http:\/\/www.cadence.com \u201d."},{"key":"19_CR36_19","unstructured":"S. Stergiou et al., \u201c\u00d7pipesLite: a Synthesis Oriented Design Library for Networks on Chips\u201d, pp. 1188-1193, Proc. DATE 2005."},{"key":"19_CR37_19","doi-asserted-by":"crossref","unstructured":"F. Angiolini et al., \u201cContrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness\u201d, pp. 124-129, Proc. DATE 2006.","DOI":"10.1109\/DATE.2006.244033"},{"key":"19_CR38_19","doi-asserted-by":"crossref","unstructured":"A. Pullini, F. Angiolini, D. Bertozzi, L. Benini, \u201cFault Tolerance Overhead in Network-on-Chip Flow Control Schemes\u201d, Proc. SBCCI, pp. 224-229, 2005.","DOI":"10.1145\/1081081.1081138"},{"key":"19_CR39_19","unstructured":"www.ocpip.org"},{"key":"19_CR40_19","doi-asserted-by":"crossref","unstructured":"D. Bertozzi et al., \u201dNoC Synthesis Flow for Customized Domain Specific Multi-Processor Systems-on-Chip\u201d, IEEE Transactions on Parallel and Distributed Sys-tems, Feb 2005.","DOI":"10.1109\/TPDS.2005.22"}],"container-title":["IFIP International Federation for Information Processing","VLSI-SoC: Research Trends in VLSI and Systems on Chip"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-0-387-74909-9_19.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,22]],"date-time":"2025-01-22T19:13:57Z","timestamp":1737573237000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-0-387-74909-9_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9780387749082"],"references-count":40,"URL":"https:\/\/doi.org\/10.1007\/978-0-387-74909-9_19","relation":{},"subject":[]}}