{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T16:36:53Z","timestamp":1776443813505,"version":"3.51.2"},"publisher-location":"Boston, MA","reference-count":26,"publisher":"Springer US","isbn-type":[{"value":"9781441969101","type":"print"},{"value":"9781441969118","type":"electronic"}],"license":[{"start":{"date-parts":[[2010,8,27]],"date-time":"2010-08-27T00:00:00Z","timestamp":1282867200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2010,8,27]],"date-time":"2010-08-27T00:00:00Z","timestamp":1282867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-1-4419-6911-8_2","type":"book-chapter","created":{"date-parts":[[2010,9,23]],"date-time":"2010-09-23T16:37:22Z","timestamp":1285259842000},"page":"21-43","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Run-Time Power-Gating Techniques for Low-Power On-Chip Networks"],"prefix":"10.1007","author":[{"given":"Hiroki","family":"Matsutani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michihiro","family":"Koibuchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroshi","family":"Nakamura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,8,27]]},"reference":[{"key":"2_CR1_2","volume-title":"Garnet: A Detailed Interconnection Network Model Inside a Full-System Simulation Framework","author":"N Agarwal","year":"2008","unstructured":"Agarwal, N., Peh, L.S., Jha, N.: Garnet: A Detailed Interconnection Network Model Inside a Full-System Simulation Framework. Tech. Rep. CE-P08-001, Princeton University (2008)"},{"key":"2_CR2_2","series-title":"Proceedings of the International Symposium on Networks-on-Chip (NOCS\u201907)","first-page":"163","volume-title":"A Power and Energy Exploration of Network-on-Chip Architectures","author":"A Banerjee","year":"2007","unstructured":"Banerjee, A., Mullins, R., Moore, S.: A Power and Energy Exploration of Network-on-Chip Architectures. In: Proceedings of the International Symposium on Networks-on-Chip (NOCS\u201907), pp. 163\u2013172 (2007)"},{"issue":"4","key":"2_CR3_2","doi-asserted-by":"publisher","first-page":"1167","DOI":"10.1109\/JSSC.2009.2014206","volume":"44","author":"E Beigne","year":"2009","unstructured":"Beigne, E., Clermidy, F., Lhermet, H., Miermont, S., Thonnart, Y., Tran, X.T., Valentian, A., Varreau, D., Vivet, P., Popon, X., Lebreton, H.: An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE Journal of Solid-State Circuits 44(4), 1167\u20131177 (2009)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2_CR4_2","series-title":"Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED\u201903)","first-page":"90","volume-title":"Leakage Power Modeling and Optimization in Interconnection Networks","author":"X Chen","year":"2003","unstructured":"Chen, X., Peh, L.S.: Leakage Power Modeling and Optimization in Interconnection Networks. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED\u201903), pp. 90\u201395 (2003)"},{"issue":"2","key":"2_CR5_2","doi-asserted-by":"publisher","first-page":"194","DOI":"10.1109\/71.127260","volume":"3","author":"WJ Dally","year":"1992","unstructured":"Dally, W.J.: Virtual-Channel Flow Control. IEEE Transactions on Parallel and Distributed Systems 3(2), 194\u2013205 (1992)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"issue":"1","key":"2_CR6_2","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1109\/40.566196","volume":"17","author":"M Galles","year":"1997","unstructured":"Galles, M.: Spider: A High Speed Network Interconnect. IEEE Micro 17(1), 34\u201339 (1997)","journal-title":"IEEE Micro"},{"key":"2_CR7_2","doi-asserted-by":"crossref","unstructured":"Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural Techniques for Power Gating of Execution Units. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED\u201904), pp. 32\u201337 (2004)","DOI":"10.1145\/1013235.1013249"},{"key":"2_CR8_2","unstructured":"IEEE Standard for Design and Verification of Low Power Integrated Circuits. IEEE Computer Society (2009)"},{"key":"2_CR9_2","doi-asserted-by":"crossref","unstructured":"Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M., Kondo, M.: Geyser-1: A MIPS R3000 CPU Core with Fine Grain Runtime Power Gating. In: Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC\u201909) (2009)","DOI":"10.1109\/ASSCC.2009.5357257"},{"key":"2_CR10_2","doi-asserted-by":"crossref","unstructured":"Ishikawa, M., Kamei, T., Kondo, Y., Yamaoka, M., Shimazaki, Y., Ozawa, M., Tamaki, S., Furuyama, M., Hoshi, T., Arakawa, F., Nishii, O., Hirose, K., Yoshioka, S., Hattori, T.: A 4500 MIPS\/W, 86 \u03bcA Resume-Standby, 11 \u03bcA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Transactions on Electronics E88-C(4), 528\u2013535 (2005)","DOI":"10.1093\/ietele\/e88-c.4.528"},{"key":"2_CR11_2","series-title":"Proceedings of the International Solid-State Circuits Conference (ISSCC\u201906)","first-page":"2200","volume-title":"Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor","author":"Y Kanno","year":"2006","unstructured":"Kanno, Y., et al.: Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. In: Proceedings of the International Solid-State Circuits Conference (ISSCC\u201906), pp. 2200\u20132209 (2006)"},{"key":"2_CR12_2","series-title":"Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201902)","first-page":"211","volume-title":"An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches","author":"C Kim","year":"2002","unstructured":"Kim, C., Burger, D., Keckler, S.W.: An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches. In: Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201902), pp. 211\u2013222 (2002)"},{"issue":"2","key":"2_CR13_2","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/2.982916","volume":"35","author":"PS Magnusson","year":"2002","unstructured":"Magnusson, P.S., et al.: Simics: A Full System Simulation Platform. IEEE Computer 35(2), 50\u201358 (2002)","journal-title":"IEEE Computer"},{"key":"2_CR14_2","series-title":"Proceedings of the International Symposium on Computer Architecture (ISCA\u201903)","first-page":"182","volume-title":"Token Coherence: Decoupling Performance and Correctness","author":"MMK Martin","year":"2003","unstructured":"Martin, M.M.K., Hill, M.D., Wood, D.A.: Token Coherence: Decoupling Performance and Correctness. In: Proceedings of the International Symposium on Computer Architecture (ISCA\u201903), pp. 182\u2013193 (2003)"},{"issue":"4","key":"2_CR15_2","doi-asserted-by":"publisher","first-page":"92","DOI":"10.1145\/1105734.1105747","volume":"33","author":"MMK Martin","year":"2005","unstructured":"Martin, M.M.K., Sorin, D.J., Beckmann, B.M., Marty, M.R., Xu, M., Alameldeen, A.R., Moore, K.E., Hill, M.D., Wood, D.A.: Multifacet General Execution-driven Multiprocessor Simulator (GEMS) Toolset. ACM SIGARCH Computer Architecture News (CAN\u201905) 33(4), 92\u201399 (2005)","journal-title":"ACM SIGARCH Computer Architecture News (CAN\u201905)"},{"key":"2_CR16_2","series-title":"Proceedings of the International Symposium on Networks-on-Chip (NOCS\u201908)","first-page":"23","volume-title":"Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks","author":"H Matsutani","year":"2008","unstructured":"Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. In: Proceedings of the International Symposium on Networks-on-Chip (NOCS\u201908), pp. 23\u201332 (2008)"},{"key":"2_CR17_2","series-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC\u201908)","first-page":"55","volume-title":"Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing","author":"H Matsutani","year":"2008","unstructured":"Matsutani, H., Koibuchi, M., Wang, D., Amano, H.: Run-Time Power Gating of On-Chip Routers Using Look-Ahead Routing. In: Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC\u201908), pp. 55\u201360 (2008)"},{"key":"2_CR18_2","series-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA\u201909)","first-page":"367","volume-title":"Prediction Router: Yet Another Low Latency On-Chip Router Architecture","author":"H Matsutani","year":"2009","unstructured":"Matsutani, H., Koibuchi, M., Amano, H., Yoshinaga, T.: Prediction Router: Yet Another Low Latency On-Chip Router Architecture. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA\u201909), pp. 367\u2013378 (2009)"},{"key":"2_CR19_2","series-title":"Proceedings of the International Symposium on Computer Architecture (ISCA\u201904)","first-page":"188","volume-title":"Low-Latency Virtual-Channel Routers for On-Chip Networks","author":"R Mullins","year":"2004","unstructured":"Mullins, R., West, A., Moore, S.: Low-Latency Virtual-Channel Routers for On-Chip Networks. In: Proceedings of the International Symposium on Computer Architecture (ISCA\u201904), pp. 188\u2013197 (2004)"},{"key":"2_CR20_2","doi-asserted-by":"crossref","unstructured":"Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Kashima, T., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M., Nakamura, H.: A Fine-Grain Dynamic Sleep Control Scheme in MIPS R3000. In: Proceedings of the International Conference on Computer Design (ICCD\u201908), pp. 612\u2013617 (2008)","DOI":"10.1109\/ICCD.2008.4751924"},{"key":"2_CR21_2","series-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA\u201903)","first-page":"79","volume-title":"Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks","author":"L Shang","year":"2003","unstructured":"Shang, L., Peh, L.S., Jha, N.K.: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In: Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA\u201903), pp. 79\u201390 (2003)"},{"issue":"3","key":"2_CR22_2","doi-asserted-by":"publisher","first-page":"393","DOI":"10.1109\/TPDS.2007.43","volume":"18","author":"V Soteriou","year":"2007","unstructured":"Soteriou, V., Peh, L.S.: Exploring the Design Space of Self-Regulating Power-Aware On\/Off Interconnection Networks. IEEE Transactions on Parallel and Distributed Systems 18(3), 393\u2013408 (2007)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"issue":"1","key":"2_CR23_2","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/L-CA.2004.5","volume":"3","author":"JM Stine","year":"2004","unstructured":"Stine, J.M., Carter, N.P.: Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. IEEE Computer Architecture Letters 3(1), 14\u201317 (2004)","journal-title":"IEEE Computer Architecture Letters"},{"key":"2_CR24_2","series-title":"Proceedings of the International Conference on Computer Design (ICCD\u201906)","volume-title":"A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals","author":"K Usami","year":"2006","unstructured":"Usami, K., Ohkubo, N.: A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. In: Proceedings of the International Conference on Computer Design (ICCD\u201906) (2006)"},{"issue":"1","key":"2_CR25_2","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1109\/JSSC.2007.910957","volume":"43","author":"SR Vangal","year":"2008","unstructured":"Vangal, S.R., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Singh, A., Jacob, T., Jain, S., Erraguntla, V., Roberts, C., Hoskote, Y., Borkar, N., Borkar, S.: An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits 43(1), 29\u201341 (2008)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"2_CR26_2","series-title":"Proceedings of the International Symposium on Computer Architecture (ISCA\u201995)","first-page":"24","volume-title":"SPLASH-2 Programs: Characterization and Methodological Considerations","author":"SC Woo","year":"1995","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: SPLASH-2 Programs: Characterization and Methodological Considerations. In: Proceedings of the International Symposium on Computer Architecture (ISCA\u201995), pp. 24\u201336 (1995)"}],"container-title":["Low Power Networks-on-Chip"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4419-6911-8_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T00:50:51Z","timestamp":1740531051000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-1-4419-6911-8_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,8,27]]},"ISBN":["9781441969101","9781441969118"],"references-count":26,"URL":"https:\/\/doi.org\/10.1007\/978-1-4419-6911-8_2","relation":{},"subject":[],"published":{"date-parts":[[2010,8,27]]},"assertion":[{"value":"27 August 2010","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}