{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T16:18:14Z","timestamp":1743092294181,"version":"3.40.3"},"publisher-location":"Boston, MA","reference-count":100,"publisher":"Springer US","isbn-type":[{"type":"print","value":"9781441974174"},{"type":"electronic","value":"9781441974181"}],"license":[{"start":{"date-parts":[[2010,10,25]],"date-time":"2010-10-25T00:00:00Z","timestamp":1287964800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2010,10,25]],"date-time":"2010-10-25T00:00:00Z","timestamp":1287964800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-1-4419-7418-1_12","type":"book-chapter","created":{"date-parts":[[2010,11,9]],"date-time":"2010-11-09T20:40:44Z","timestamp":1289335244000},"page":"381-432","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging"],"prefix":"10.1007","author":[{"given":"Benjamin","family":"Gojman","sequence":"first","affiliation":[]},{"given":"Nikil","family":"Mehta","sequence":"additional","affiliation":[]},{"given":"Raphael","family":"Rubin","sequence":"additional","affiliation":[]},{"given":"Andr\u00e9","family":"DeHon","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2010,10,25]]},"reference":[{"key":"12_CR1","unstructured":"ITRS (2008) International technology roadmap for semiconductors. <http:\/\/www.itrs.net\/Links\/2008ITRS\/Home2008.htm>"},{"key":"12_CR2","unstructured":"Luu J, Jamieson P, Kuon I, Betz V, Marquardat A, Rose J (2008) VPR and T-VPack: versatile Packing, Placement and Routing for FPGAs. <http:\/\/www.eecg.utoronto.ca\/vpr\/>"},{"issue":"4","key":"12_CR3","doi-asserted-by":"publisher","first-page":"237","DOI":"10.1016\/0020-0190(91)90195-N","volume":"37","author":"H Alt","year":"1991","unstructured":"Alt H, Blum N, Mehlhorn K, Paul M (1991) Computing a maximum cardinality matching in a bipartite graph in time o(n1.5\u00a0pm\/log (n)). Inf Process Lett 37(4):237\u2013240. doi: http:\/\/dx.doi.org\/10.1016\/0020-0190(91)90195-N","journal-title":"Inf Process Lett"},{"key":"12_CR4","unstructured":"Asadi GH, Tahoori MB (2005) Soft error mitigation for SRAM-based FPGAs. In: Proceedings of the VLSI Test Symposium, pp 207\u2013212"},{"issue":"12","key":"12_CR5","doi-asserted-by":"publisher","first-page":"2505","DOI":"10.1109\/16.735728","volume":"45","author":"A Asenov","year":"1998","unstructured":"Asenov A (1998) Random dopant induced threshold voltage lowering and fluctuations in sub- 0.1\u00a0\u03bcm MOSFET\u2019s: A 3-D \u201catomistic\u201d simulation study. IEEE Trans Electron Devices 45(12):2505\u20132513","journal-title":"IEEE Trans Electron Devices"},{"issue":"1","key":"12_CR6","doi-asserted-by":"publisher","first-page":"112","DOI":"10.1109\/16.974757","volume":"49","author":"A Asenov","year":"2002","unstructured":"Asenov A (2002) Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variation. IEEE Trans Electron Devices 49(1):112\u2013119","journal-title":"IEEE Trans Electron Devices"},{"issue":"5","key":"12_CR7","doi-asserted-by":"publisher","first-page":"1254","DOI":"10.1109\/TED.2003.813457","volume":"50","author":"A Asenov","year":"2003","unstructured":"Asenov A, Kaya S, Brown AR (2003) Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE Trans Electron Devices 50(5):1254\u20131260","journal-title":"IEEE Trans Electron Devices"},{"issue":"4","key":"12_CR8","doi-asserted-by":"publisher","first-page":"675","DOI":"10.1109\/TVLSI.2009.2014559","volume":"18","author":"M Ashoue","year":"2010","unstructured":"Ashoue M, Chatterjee A, Singh DA (2010) Post-manufacture tuning for Nano-CMOS yield recovery using reconfigurable logic. IEEE Trans VLSI Syst 18(4):675\u2013679. doi: 10.1109\/TVLSI.2009.2014559","journal-title":"IEEE Trans VLSI Syst"},{"issue":"3","key":"12_CR9","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1109\/MC.2004.1274005","volume":"37","author":"T Austin","year":"2004","unstructured":"Austin T, Blaauw D, Mudge T, Flautner K (2004) Making typical silicon matter with Razor. IEEE Compu 37(3):57\u201365","journal-title":"IEEE Compu"},{"key":"12_CR10","unstructured":"Betz V, Rose J (1999) FPGA place-and-route challenge. <http:\/\/www.eecg.toronto.edu\/vaughn\/challenge\/challenge.html>"},{"key":"12_CR11","doi-asserted-by":"crossref","unstructured":"Bijansky S, Aziz A (2008) TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. In: Proceedings of the ACM\/IEEE Design Automation Conference","DOI":"10.1145\/1391469.1391672"},{"key":"12_CR12","doi-asserted-by":"crossref","unstructured":"Boning D, Panganiban J, Gonzalez-Valentin K, Nassif S, McDowell C, Gattiker A, Liu F (2002) Test structures for delay variability. In: Proceedings of the international workshop on timing issues in the specification and synthesis of digital systems. ACM, New York, NY, pp 109","DOI":"10.1145\/589411.589435"},{"issue":"7290","key":"12_CR13","doi-asserted-by":"publisher","first-page":"873","DOI":"10.1038\/nature08940","volume":"464","author":"J Borghetti","year":"2010","unstructured":"Borghetti J, Snider GS, Kuekes PJ, Yang JJ, Stewart DR, Williams RS (2010) \u2018Memristive\u2019 switches enable \u2018stateful\u2019 logic operations via material implication. Nature 464(7290):873\u2013876. doi: 10.1038\/nature08940. URL http:\/\/dx.doi.org\/10.1038\/nature08940","journal-title":"Nature"},{"issue":"1","key":"12_CR14","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1109\/JSSC.2008.2007148","volume":"44","author":"KA Bowman","year":"2009","unstructured":"Bowman KA, Tschanz JW, Kim NS, Lee JC, Wilkerson CB, Lu SLL, Karnik T, De VK (2009) Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance. IEEE J Solid State Circuits 44(1):49\u201363","journal-title":"IEEE J Solid State Circuits"},{"issue":"4","key":"12_CR15","doi-asserted-by":"publisher","first-page":"1924","DOI":"10.1021\/la990791m","volume":"16","author":"CL Brown","year":"2000","unstructured":"Brown CL, Jonas U, Preece JA, Ringsdorf H, Seitz M, Stoddart JF (2000) Introduction of [2]catenanes into langmuir films and langmuir-blodgett multilayers. a possible strategy for molecular information storage materials. Langmuir 16(4):1924\u20131930","journal-title":"Langmuir"},{"issue":"10","key":"12_CR16","doi-asserted-by":"publisher","first-page":"1866","DOI":"10.1109\/TCAD.2007.895613","volume":"26","author":"Y Cao","year":"2007","unstructured":"Cao Y, Clark L (2007) Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. IEEE Trans Comput-Aided Des Integr Circ Syst 26(10):1866\u20131873","journal-title":"IEEE Trans Comput-Aided Des Integr Circ Syst"},{"key":"12_CR17","doi-asserted-by":"publisher","first-page":"462","DOI":"10.1088\/0957-4484\/14\/4\/311","volume":"14","author":"Y Chen","year":"2003","unstructured":"Chen Y, Jung GY, Ohlberg DAA, Li X, Stewart DR, Jeppesen JO, Nielsen KA, Stoddart JF, Williams RS (2003) Nanoscale molecular-switch crossbar circuits. Nanotechnology 14:462\u2013468","journal-title":"Nanotechnology"},{"issue":"10","key":"12_CR18","doi-asserted-by":"publisher","first-page":"1610","DOI":"10.1063\/1.1559439","volume":"82","author":"Y Chen","year":"2003","unstructured":"Chen Y, Ohlberg DAA, Li X, Stewart DR, Williams RS, Jeppesen JO, Nielsen KA, Stoddart JF, Olynick DL, Anderson E (2003) Nanoscale molecular-switch devices fabricated by imprint lithography. Appl Phys Lett 82(10):1610\u20131612","journal-title":"Appl Phys Lett"},{"key":"12_CR19","doi-asserted-by":"crossref","unstructured":"Cheng L, Xiong J, He L, Hutton M (2006) FPGA performance optimization via chipwise placement considering process variations. In: Proceedings of the international conference on field-programmable logic and applications, pp 1\u20136","DOI":"10.1109\/FPL.2006.311193"},{"key":"12_CR20","doi-asserted-by":"publisher","first-page":"1172","DOI":"10.1126\/science.289.5482.1172","volume":"289","author":"C Collier","year":"2000","unstructured":"Collier C, Mattersteig G, Wong E, Luo Y, Beverly K, Sampaio J, Raymo F, Stoddart J, Heath J (2000) A [2]Catenane-Based Solid State Reconfigurable Switch. Science 289:1172\u20131175","journal-title":"Science"},{"key":"12_CR21","unstructured":"Committee I.S. (1990) IEEE standard test access port and boundary-scan architecture. IEEE, 345 East 47th Street, New York, NY 10017-2394. IEEE Std 1149.1-1990"},{"key":"12_CR22","unstructured":"Cormen T, Leiserson C, Rivest R (1990) Introduction to Algorithms. MIT Press and McGraw, Cambridge, Massachusetts, New York."},{"issue":"15","key":"12_CR23","doi-asserted-by":"publisher","first-page":"2214","DOI":"10.1063\/1.1363692","volume":"78","author":"Y Cui","year":"2001","unstructured":"Cui Y, Lauhon LJ, Gudiksen MS, Wang J, Lieber CM (2001) Diameter-controlled synthesis of single crystal silicon nanowires. Appled Phys Lett 78(15):2214\u20132216","journal-title":"Appled Phys Lett"},{"key":"12_CR24","doi-asserted-by":"crossref","unstructured":"Culbertson WB, Amerson R, Carter R, Kuekes P, Snider G (1997) Defect tolerance on the TERAMAC custom computer. In: Proceedings of the IEEE symposium on FPGAs for custom computing machines, pp 116\u2013123","DOI":"10.1109\/FPGA.1997.624611"},{"key":"12_CR25","doi-asserted-by":"crossref","unstructured":"DeHon A (2005) Design of programmable interconnect for sublithographic programmable logic arrays. in: proceedings of the international symposium on field-programmable gate arrays, pp 127\u2013137","DOI":"10.1145\/1046192.1046210"},{"issue":"2","key":"12_CR26","doi-asserted-by":"publisher","first-page":"109","DOI":"10.1145\/1084748.1084750","volume":"1","author":"A DeHon","year":"2005","unstructured":"DeHon A (2005) Nanowire-based programmable architectures. ACM J Emerg Technol Comput Syst 1(2):109\u2013162. doi: http:\/\/doi.acm.org\/10.1145\/1084748.1084750","journal-title":"ACM J Emerg Technol Comput Syst"},{"key":"12_CR27","doi-asserted-by":"crossref","unstructured":"DeHon A (2008) The case for reconfigurable components with logic scrubbing: regular hygiene keeps logic FIT (low). In: Proceedings of the international workshop on design and test of nano devices, circuits, and systems, pp 67\u201370","DOI":"10.1109\/NDCS.2008.17"},{"key":"12_CR28","doi-asserted-by":"crossref","unstructured":"DeHon A, Likharev KK (2005) Hybrid CMOS\/nanoelectronic digital circuits: Devices, architectures, and design automation. In: Proceedings of the international conference on computer aided design, pp 375\u2013382","DOI":"10.1109\/ICCAD.2005.1560097"},{"issue":"3","key":"12_CR29","doi-asserted-by":"publisher","first-page":"165","DOI":"10.1109\/TNANO.2003.816658","volume":"2","author":"A DeHon","year":"2003","unstructured":"DeHon A, Lincoln P, Savage J (2003) Stochastic assembly of sublithographic nanoscale interfaces. IEEE Trans Nanotechnol 2(3):165\u2013174","journal-title":"IEEE Trans Nanotechnol"},{"issue":"4","key":"12_CR30","doi-asserted-by":"publisher","first-page":"306","DOI":"10.1109\/MDT.2005.94","volume":"22","author":"A DeHon","year":"2005","unstructured":"DeHon A, Naeimi H (2005) Seven strategies for tolerating highly defective fabrication. IEEE Des Test Comput 22(4):306\u2013315","journal-title":"IEEE Des Test Comput"},{"key":"12_CR31","doi-asserted-by":"crossref","unstructured":"DeHon A, Wilson MJ (2004) Nanowire-based sublithographic programmable logic arrays. In: Proceedings of the international symposium on field-programmable gate arrays, pp 123\u2013132","DOI":"10.1145\/968280.968299"},{"issue":"2","key":"12_CR32","doi-asserted-by":"crossref","first-page":"386","DOI":"10.1021\/nl073224p","volume":"8","author":"Y Dong","year":"2008","unstructured":"Dong Y, Yu G, McAlpine MC, Lu W, Lieber CM (2008) Si\/a-Si core\/shell nanowires as nonvolatile crossbar switches. Nanoletters 8(2):386\u2013391","journal-title":"Nanoletters"},{"key":"12_CR33","doi-asserted-by":"crossref","unstructured":"Emmert J, Stroud C, Skaggs B, Abramovici M (2000) Dynamic fault tolerance in FPGAs via partial reconfiguration. In: Proceedings of the IEEE symposium on field-programmable custom computing machines, pp 165\u2013174","DOI":"10.1109\/FPGA.2000.903403"},{"issue":"2","key":"12_CR34","doi-asserted-by":"publisher","first-page":"238","DOI":"10.1109\/TNANO.2004.837852","volume":"4","author":"Z Fan","year":"2005","unstructured":"Fan Z, Mo X, Lou C, Yao Y, Wang D, Chen G, Lu JG (2005) Structures and electrical properties for Ag-tetracyanoquinodimetheane organometallic nanowires. IEEE Trans Nanotechnol 4(2):238\u2013241","journal-title":"IEEE Trans Nanotechnol"},{"key":"12_CR35","unstructured":"Gojman B (2010) Algorithms and techniques for conquering extreme physical variation in bottomup nanoscale systems. Master\u2019s thesis, California Institute of Technology. http:\/\/resolver.caltech.edu\/CaltechTHESIS:04052010-152122284"},{"key":"12_CR36","doi-asserted-by":"crossref","unstructured":"Gojman B, DeHon A (2009) VMATCH: using logical variation to counteract physical variation in bottom-up, nanoscale systems. In: Proceedings of the international conference on field-programmable technology, pp 78\u201387. IEEE","DOI":"10.1109\/FPT.2009.5377684"},{"issue":"6","key":"12_CR37","doi-asserted-by":"publisher","first-page":"625","DOI":"10.1049\/iet-cdt.2008.0128","volume":"3","author":"B Gojman","year":"2009","unstructured":"Gojman B, Manem H, Rose GS, DeHon A (2009) Inversion schemes for sublithographic programmable logic arrays. IET Comput Digit Tech 3(6):625\u2013642","journal-title":"IET Comput Digit Tech"},{"key":"12_CR38","doi-asserted-by":"crossref","unstructured":"Goldstein SC, Budiu M (2001) NanoFabrics: spatial computing using molecular electronics. In: Proceedings of the international symposium on computer architecture, pp 178\u2013189","DOI":"10.1145\/384285.379262"},{"key":"12_CR39","doi-asserted-by":"crossref","unstructured":"Goldstein SC, Rosewater D (2002) Digital logic using molecular electronics. In: ISSCC digest of technical papers, pp 204\u2013205. IEEE","DOI":"10.1109\/ISSCC.2002.993007"},{"key":"12_CR40","doi-asserted-by":"publisher","first-page":"414","DOI":"10.1038\/nature05462","volume":"445","author":"JE Green","year":"2007","unstructured":"Green JE, Choi JW, Boukai A, Bunimovich Y, Johnston-Halperin E, DeIonno E, Luo Y, Sheriff BA, Xu K, Shin YS, Tseng HR, Stoddart JF, Heath JR (2007) A 160- kilobit molecular electronic memory patterned at 1011 bits per square centimetre. Nature 445:414\u2013417","journal-title":"Nature"},{"key":"12_CR41","doi-asserted-by":"publisher","first-page":"617","DOI":"10.1038\/415617a","volume":"415","author":"MS Gudiksen","year":"2002","unstructured":"Gudiksen MS, Lauhon LJ, Wang J, Smith DC, Lieber CM (2002) Growth of nanowire superlattice structures for nanoscale photonics and electronics. Nature 415:617\u2013620","journal-title":"Nature"},{"key":"12_CR42","doi-asserted-by":"publisher","first-page":"4062","DOI":"10.1021\/jp010540y","volume":"105","author":"MS Gudiksen","year":"2001","unstructured":"Gudiksen MS, Wang J, Lieber CM (2001) Synthetic control of the diameter and length of semiconductor nanowires. J Phys Chem B 105:4062\u20134064","journal-title":"J Phys Chem B"},{"issue":"4\u20135","key":"12_CR43","doi-asserted-by":"publisher","first-page":"469","DOI":"10.1147\/rd.504.0469","volume":"50","author":"S Hanson","year":"2006","unstructured":"Hanson S, Zhai B, Bernstein K, Blaauw D, Bryant A, Chang L, Das KK, Haensch W, Nowak EJ, Sylvester DM (2006) Ultralow-voltage, minimum-energy CMOS. IBM J Res Dev 50(4\u20135):469\u2013490","journal-title":"IBM J Res Dev"},{"key":"12_CR44","unstructured":"Hauck S, DeHon A (eds) (2008) Reconfigurable computing: the theory and practice of FPGA based computation. Systems-on-Silicon. Elsevier, Burlington, MA"},{"issue":"5370","key":"12_CR45","doi-asserted-by":"publisher","first-page":"1716","DOI":"10.1126\/science.280.5370.1716","volume":"280","author":"JR Heath","year":"1998","unstructured":"Heath JR, Kuekes PJ, Snider GS, Williams RS (1998) A defect-tolerant computer architecture: opportunities for nanotechnology. Science 280(5370):1716\u20131721","journal-title":"Science"},{"issue":"4","key":"12_CR46","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1137\/0202019","volume":"2","author":"JE Hopcroft","year":"1973","unstructured":"Hopcroft JE, Karp RM (1973) An n2.5 algorithm for maximum matching in bipartite graphs. SIAM J Comput 2(4):225\u2013231","journal-title":"SIAM J Comput"},{"key":"12_CR47","doi-asserted-by":"publisher","first-page":"630","DOI":"10.1126\/science.291.5504.630","volume":"291","author":"Y Huang","year":"2001","unstructured":"Huang Y, Duan X, Wei Q, Lieber CM (2001) Directed assembly of one-dimensional nanostructures into functional networks. Science 291:630\u2013633","journal-title":"Science"},{"key":"12_CR48","unstructured":"Katsuki K, Kotani M, Kobayashi K, Onodera H (2005) A yield and speed enhancement scheme under within-die variations on 90\u00a0nm LUT array. In: Proceedings of the IEEE custom integrated circuits conference, pp 601\u2013604"},{"issue":"4","key":"12_CR49","first-page":"96","volume":"0","author":"G Krishnan","year":"2005","unstructured":"Krishnan G (2005) Flexibility with EasyPath FPGAs. Xcell J 55:96\u201398","journal-title":"Xcell J"},{"issue":"2","key":"12_CR50","doi-asserted-by":"publisher","first-page":"212","DOI":"10.1109\/92.678870","volume":"26","author":"J Lach","year":"1998","unstructured":"Lach J, Mangione-Smith WH, Potkonjak M (1998) Low overhead fault-tolerant FPGA systems. IEEE Trans VLSI Syst 26(2):212\u2013221","journal-title":"IEEE Trans VLSI Syst"},{"key":"12_CR51","doi-asserted-by":"crossref","unstructured":"Lakamraju V, Tessier R (2000) Tolerating operational faults in cluster-based FPGAs. In: Proceedings of the international symposium on field-programmable gate arrays, pp 187\u2013194","DOI":"10.1145\/329166.329205"},{"key":"12_CR52","doi-asserted-by":"publisher","first-page":"57","DOI":"10.1038\/nature01141","volume":"420","author":"LJ Lauhon","year":"2002","unstructured":"Lauhon LJ, Gudiksen MS, Wang D, Lieber CM (2002) Epitaxial core-shell and core-multishell nanowire heterostructures. Nature 420:57\u201361","journal-title":"Nature"},{"key":"12_CR53","doi-asserted-by":"publisher","first-page":"83","DOI":"10.1146\/annurev.matsci.34.040203.112300","volume":"34","author":"M Law","year":"2004","unstructured":"Law M, Goldberger J, Yang P (2004) Semiconductor nanowires and nanotubes. Annu Rev Mater Sci 34:83\u2013122","journal-title":"Annu Rev Mater Sci"},{"key":"12_CR54","doi-asserted-by":"crossref","unstructured":"Lewis D, Ahmed E, Baeckler G, Betz V, Bourgeault M, Cashman D, Galloway D, Hutton M, Lane C, Lee A, Leventis P, Marquardt S, McClintock C, Padalia K, Pedersen B, Powell G, Ratchev B, Reddy S, Schleicher J, Stevens K, Yuan R, Cliff R, Rose J (2005) The Stratix-II logic and routing architecture. In: Proceedings of the international symposium on field-programmable gate arrays, pp 14\u201320","DOI":"10.1145\/1046192.1046195"},{"key":"12_CR55","doi-asserted-by":"crossref","unstructured":"Lewis D, Betz V, Jefferson D, Lee A, Lane C, Leventis P, Marquardt S, McClintock C, Pedersen B, Powell G, Reddy S, Wysocki C, Cliff R, Rose J (2003) The Stratix routing and logic architecture. In: Proceedings of the international symposium on field- programmable gate arrays, pp 12\u201320","DOI":"10.1145\/611817.611821"},{"key":"12_CR56","doi-asserted-by":"crossref","unstructured":"Li ML, Ramachandran P, Sahoo SK, Adve SV, Adve VS, Zhou Y (2008) Understanding the propagation of hard errors to software and implications for resilient system design. In: Proceedings of the international conference on architectural support for programming languages and operating systems, pp 265\u2013276","DOI":"10.1145\/1353535.1346315"},{"issue":"5","key":"12_CR57","doi-asserted-by":"publisher","first-page":"17","DOI":"10.1109\/MDT.2003.1232252","volume":"20","author":"X Lin","year":"2003","unstructured":"Lin X, Press R, Rajski J, Reuter P, Rinderknecht T, Swanson B, Tamarapalli N (2003) High-frequency, at-speed scan testing. IEEE Des Test Comput 20(5):17\u201325","journal-title":"IEEE Des Test Comput"},{"key":"12_CR58","unstructured":"Ling ZM, Cho J, Wells RW, Johnson CS, Davis SG (2003) Method of using partially defective programmable logic devices. US Patent 6,664,808"},{"issue":"6","key":"12_CR59","doi-asserted-by":"publisher","first-page":"519","DOI":"10.1002\/1439-7641(20020617)3:6<519::AID-CPHC519>3.0.CO;2-2","volume":"3","author":"Y Luo","year":"2002","unstructured":"Luo Y, Collier P, Jeppesen JO, Nielsen KA, Delonno E, Ho G, Perkins J, Tseng HR, Yamamoto T, Stoddart JF, Heath JR (2002) Two-dimensional molecular electronics circuits. ChemPhysChem 3(6):519\u2013525","journal-title":"ChemPhysChem"},{"key":"12_CR60","doi-asserted-by":"crossref","unstructured":"Matsumoto Y, Hioki M, Koike TKH, Tsutsumi T, Nakagawa T, Sekigawa T (2008) Suppression of intrinsic delay variation in FPGAs using multiple configurations. Trans Reconfig Technol Syst 1(1). Doi: http:\/\/doi.acm.org\/10.1145\/1331897.1331899","DOI":"10.1145\/1331897.1331899"},{"key":"12_CR61","doi-asserted-by":"crossref","unstructured":"McMurchie L, Ebeling C (1995) PathFinder: a negotiation-based performance-driven router for FPGAs. In: Proceedings of the international symposium on field-programmable gate arrays, ACM, pp 111\u2013117","DOI":"10.1109\/FPGA.1995.242049"},{"key":"12_CR62","doi-asserted-by":"crossref","unstructured":"Nabaaz G, Aziziy N, Najm FN (2006) An adaptive FPGA architecture with process variation compensation and reduced leakage. In: Proceedings of the ACM\/IEEE design automation conference, pp 624\u2013629","DOI":"10.1145\/1146909.1147069"},{"key":"12_CR63","doi-asserted-by":"crossref","unstructured":"Naeimi H, DeHon A (2004) A greedy algorithm for tolerating defective crosspoints in NanoPLA design. In: Proceedings of the international conference on field-programmable technology, IEEE pp 49\u201356","DOI":"10.1109\/FPT.2004.1393250"},{"key":"12_CR64","doi-asserted-by":"crossref","unstructured":"Nagaraj K, Kundu S (2009) Process variation mitigation via post silicon clock tuning. In: Proceedings of the Great Lakes symposium on VLSI, pp 227\u2013232","DOI":"10.1145\/1531542.1531598"},{"key":"12_CR65","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-2142-3","volume-title":"The boundary-scan handbook.","author":"KP Parker","year":"1992","unstructured":"Parker KP (1992) The boundary-scan handbook. Kluwer, Norwell, MA"},{"key":"12_CR66","unstructured":"Paul S, Bhunia S (2008) MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices. In: Proceedings of the Asia and South Pacific design automation conference, pp 77\u201382"},{"key":"12_CR67","unstructured":"Paul S, Chatterjee S, Mukhopadhyay S, Bhunia S (2009) Nanoscale reconfigurable computing using non-volatile 2-d sttram array. In: Proceedings fo the IEEE international conference on nanotechnology"},{"key":"12_CR68","first-page":"524,114","volume":"5","author":"SF Peng","year":"1996","unstructured":"Peng SF (1996) Method and apparatus for testing semiconductor devices at speed. US Patent 5,524,114","journal-title":"US Patent"},{"key":"12_CR69","unstructured":"Rabaey JM, Chandrakasan A, Nikolic B (1999) Digital integrated circuits, 2nd edn. Prentice Hall, Upper Saddle River, New Jersey"},{"issue":"7","key":"12_CR70","doi-asserted-by":"crossref","first-page":"1407","DOI":"10.1021\/nl050747t","volume":"5","author":"PV Radovanovic","year":"2005","unstructured":"Radovanovic PV, Barrelet CJ, Gradecak S, Qian F, Lieber CM (2005) General syntehsis of manganese-doped II-VI and III-V semiconductor nanowires. Nanoletters 5(7):1407\u20131411","journal-title":"Nanoletters"},{"issue":"11","key":"12_CR71","doi-asserted-by":"publisher","first-page":"2380","DOI":"10.1109\/TCSI.2007.907860","volume":"54","author":"GS Rose","year":"2007","unstructured":"Rose GS, Stan MR (2007) A programmable majority logic array using molecular scale electronics. IEEE Trans Circuits Syst I Fundam Theory Appl 54(11):2380\u20132390","journal-title":"IEEE Trans Circuits Syst I Fundam Theory Appl"},{"key":"12_CR72","doi-asserted-by":"crossref","unstructured":"Rubin R, DeHon A (2009) Choose-your-own-adventure routing: lightweight load-time defect avoidance. In: Proceedings of the international symposium on field-programmable gate arrays, pp 23\u201332","DOI":"10.1145\/1508128.1508133"},{"key":"12_CR73","doi-asserted-by":"crossref","unstructured":"Sahoo SK, Li ML, Ramachandran P, Adve SV, Adve VS, Zhou Y (2008) Using likely program invariants to detect hardware errors. In: Proceedings of the international conference on dependable systems and networks, pp 70\u201379","DOI":"10.1109\/DSN.2008.4630072"},{"issue":"1","key":"12_CR74","doi-asserted-by":"publisher","first-page":"114","DOI":"10.1109\/24.52622","volume":"39","author":"A Saleh","year":"1990","unstructured":"Saleh A, Serrano J, Patel J (1990) Reliability of scrubbing recovery-techniques for memory systems. IEEE Trans Reliab 39(1):114\u2013122","journal-title":"IEEE Trans Reliab"},{"key":"12_CR75","doi-asserted-by":"crossref","unstructured":"Saxena J, Butler KM, Gatt J, Raghuraman R, Kumar SP, Basu S, Campbell DJ, Berech J (2002) Scan-based transition fault testing \u2013 implementation and low cost test challenges. Proceedings of international test conference pp 1120\u20131129. doi: 10.1109\/TEST.2002.1041869","DOI":"10.1109\/TEST.2002.1041869"},{"key":"12_CR76","doi-asserted-by":"crossref","unstructured":"Sedcole P, Cheung PYK (2006) Within-die delay variability in 90\u00a0nm FPGAs and beyond. In: Proceedings of the international conference on field-programmable technology, pp 97\u2013104","DOI":"10.1109\/FPT.2006.270300"},{"key":"12_CR77","doi-asserted-by":"crossref","unstructured":"Sedcole P, Cheung PYK (2008) Parametric yield modeling and simulations of FPGA circuits considering within-die delay variations. Trans Reconfig Technol Syst 1(2). doi: 10.1145\/1371579.1371582","DOI":"10.1145\/1371579.1371582"},{"key":"12_CR78","doi-asserted-by":"crossref","unstructured":"Sinha SK, Kamarchik PM, Goldstein SC (2000) Tunable fault tolerance for runtime reconfigurable architectures. In: Proceedings of the IEEE symposium on field-programmable custom computing machines, pp 185\u2013192","DOI":"10.1109\/FPGA.2000.903405"},{"issue":"1","key":"12_CR79","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1331897.1331900","volume":"1","author":"S Sivaswamy","year":"2008","unstructured":"Sivaswamy S, Bazargan K (2008) Statistical analysis and process variation-aware routing and skew assignment for FPGAs. Trans Reconfig Technol Syst 1(1):1\u201335. doi: http:\/\/doi.acm.org\/10.1145\/1331897.1331900","journal-title":"Trans Reconfig Technol Syst"},{"key":"12_CR80","doi-asserted-by":"publisher","first-page":"881","DOI":"10.1088\/0957-4484\/15\/8\/003","volume":"15","author":"G Snider","year":"2004","unstructured":"Snider G, Kuekes P, Williams RS (2004) CMOS-like logic in defective, nanoscale crossbars. Nanotechnology 15:881\u2013891","journal-title":"Nanotechnology"},{"key":"12_CR81","doi-asserted-by":"crossref","unstructured":"Snider GS, Williams RS (2007) Nano\/CMOS architetures using a field-programmable nanowire interconnect. Nanotechnology 18(3)","DOI":"10.1088\/0957-4484\/18\/3\/035204"},{"key":"12_CR82","unstructured":"Steiner N (2008) Autonomous computing systems. Ph.D. thesis, Virginia Polytechnic Institute and State University. Available Online: 10.1109\/AERO.2009.4839512"},{"key":"12_CR83","doi-asserted-by":"crossref","unstructured":"Steiner N, Athanas P (2009) Hardware autonomy and space systems. In: Proceedings of the IEEE aerospace conference, pp 1\u201313","DOI":"10.1109\/AERO.2009.4839512"},{"issue":"6","key":"12_CR84","doi-asserted-by":"publisher","first-page":"888","DOI":"10.1088\/0957-4484\/16\/6\/045","volume":"16","author":"DB Strukov","year":"2005","unstructured":"Strukov DB, Likharev KK (2005) CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16(6):888\u2013900","journal-title":"Nanotechnology"},{"issue":"9","key":"12_CR85","doi-asserted-by":"publisher","first-page":"1926","DOI":"10.1109\/TED.2003.816523","volume":"50","author":"VA Sverdlov","year":"2003","unstructured":"Sverdlov VA, Walls TJ, Likharev KK (2003) Nanoscale silicon MOSFETs: a theoretical study. IEEE Trans Electron Devices 50(9):1926\u20131933","journal-title":"IEEE Trans Electron Devices"},{"issue":"4","key":"12_CR86","doi-asserted-by":"publisher","first-page":"636","DOI":"10.1109\/JSSC.2004.825121","volume":"39","author":"S Tam","year":"2004","unstructured":"Tam S, Limaye RD, Desai UN (2004) Clock generation and distribution for the 130-nm Itanium 2 processor with 6-MB on-die L3 cache. IEEE J Solid State Circuits 39(4):636\u2013642","journal-title":"IEEE J Solid State Circuits"},{"key":"12_CR87","first-page":"424","volume":"7","author":"SM Trimberger","year":"2008","unstructured":"Trimberger SM (2008) Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits. US Patent 7,424,655","journal-title":"US Patent"},{"key":"12_CR88","doi-asserted-by":"publisher","first-page":"8902","DOI":"10.1021\/ja803408f","volume":"130","author":"C Wang","year":"2008","unstructured":"Wang C, Hu Y, Lieber CM, Sun S (2008) Ultrathin Au nanowires and their transport properties. J Am Chem Soc 130: 8902\u20138903","journal-title":"J Am Chem Soc"},{"key":"12_CR89","first-page":"817,006","volume":"6","author":"RW Wells","year":"2004","unstructured":"Wells RW, Ling ZM, Patrie RD, Tong VL, Cho J, Toutounchi S (2004) Applicationspecific testing methods for programmable logic devices. US Patent 6,817,006","journal-title":"US Patent"},{"issue":"7","key":"12_CR90","doi-asserted-by":"crossref","first-page":"951","DOI":"10.1021\/nl034268a","volume":"3","author":"D Whang","year":"2003","unstructured":"Whang D, Jin S, Lieber CM (2003) Nanolithography using hierarchically assembled nanowire masks. Nanoletters 3(7):951\u2013954","journal-title":"Nanoletters"},{"issue":"9","key":"12_CR91","doi-asserted-by":"crossref","first-page":"1255","DOI":"10.1021\/nl0345062","volume":"3","author":"D Whang","year":"2003","unstructured":"Whang D, Jin S, Wu Y, Lieber CM (2003) Large-scale hierarchical organization of nanowire arrays for integrated nanosystems. Nanoletters 3(9):1255\u20131259","journal-title":"Nanoletters"},{"key":"12_CR92","first-page":"256","volume":"6","author":"S Williams","year":"2001","unstructured":"Williams S, Kuekes P (2001) Demultiplexer for a molecular wire crossbar network. US Patent 6,256,767","journal-title":"US Patent"},{"issue":"2","key":"12_CR93","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1534916.1534920","volume":"2","author":"JSJ Wong","year":"2009","unstructured":"Wong JSJ, Sedcole P, Cheung PYK (2009) Self-measurement of combinatorial circuit delays in FPGAs. Trans Reconfig Technol Syst 2(2):1\u201322","journal-title":"Trans Reconfig Technol Syst"},{"key":"12_CR94","doi-asserted-by":"publisher","first-page":"1173","DOI":"10.1007\/s00339-004-3176-y","volume":"80","author":"W Wu","year":"2005","unstructured":"Wu W, Jung GY, Olynick D, Straznicky J, Li Z, Li X, Ohlberg D, Chen Y, Wang S-Y, Liddle J, Tong W, Williams RS (2005) One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography. Appl Phy A 80:1173\u20131178","journal-title":"Appl Phy A"},{"key":"12_CR95","unstructured":"Xilinx, Inc. (2005) 2100 Logic Drive, San Jose, CA 95124 Xilinx Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet. DS083 http:\/\/direct.xilinx.com\/bvdocs\/publications\/ds083.pdf"},{"key":"12_CR96","unstructured":"Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124 (2005) Virtex FPGA Series Configuration and Readback. XAPP 138 http:\/\/www.xilinx.com\/bvdocs\/appnotes\/xapp138.pdf"},{"key":"12_CR97","unstructured":"Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124 (2008) Virtex-5 FPGA Configuration User Guide. UG191 http:\/\/www.xilinx.com\/bvdocs\/userguides\/ug191.pdf"},{"key":"12_CR98","doi-asserted-by":"publisher","first-page":"1304","DOI":"10.1126\/science.1118798","volume":"310","author":"C Yang","year":"2005","unstructured":"Yang C, Zhong Z, Lieber CM (2005) Encoding electronic properties by synthesis of axial modulation-doped silicon nanowires. Science 310:1304\u20131307","journal-title":"Science"},{"issue":"6","key":"12_CR99","doi-asserted-by":"publisher","first-page":"372","DOI":"10.1038\/nnano.2007.150","volume":"2","author":"G Yu","year":"2007","unstructured":"Yu G, Cao A, Lieber CM (2007) Large-area blown bubble films of aligned nanowires and carbon nanotubes. Nat Nanotechnol 2(6):372\u2013377. doi: 10.1038\/nnano.2007.150","journal-title":"Nat Nanotechnol"},{"issue":"11","key":"12_CR100","doi-asserted-by":"publisher","first-page":"2816","DOI":"10.1109\/TED.2006.884077","volume":"53","author":"W Zhao","year":"2006","unstructured":"Zhao W, Cao Y (2006) New generation of predictive technology model for sub-45\u00a0nm early design exploration. IEEE Trans Electron Devices 53(11):2816\u20132823","journal-title":"IEEE Trans Electron Devices"}],"container-title":["Low-Power Variation-Tolerant Design in Nanometer Silicon"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4419-7418-1_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,27]],"date-time":"2025-02-27T18:28:17Z","timestamp":1740680897000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-1-4419-7418-1_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10,25]]},"ISBN":["9781441974174","9781441974181"],"references-count":100,"URL":"https:\/\/doi.org\/10.1007\/978-1-4419-7418-1_12","relation":{},"subject":[],"published":{"date-parts":[[2010,10,25]]},"assertion":[{"value":"25 October 2010","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}