{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,28]],"date-time":"2025-02-28T05:32:32Z","timestamp":1740720752257,"version":"3.38.0"},"publisher-location":"New York, NY","reference-count":30,"publisher":"Springer New York","isbn-type":[{"type":"print","value":"9781441976178"},{"type":"electronic","value":"9781441976185"}],"license":[{"start":{"date-parts":[[2010,11,6]],"date-time":"2010-11-06T00:00:00Z","timestamp":1289001600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-1-4419-7618-5_11","type":"book-chapter","created":{"date-parts":[[2010,11,5]],"date-time":"2010-11-05T15:52:13Z","timestamp":1288972333000},"page":"249-271","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Influence of Stacked 3D Memory\/Cache Architectures on GPUs"],"prefix":"10.1007","author":[{"given":"Ahmed","family":"Al Maashri","sequence":"first","affiliation":[]},{"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Xiangyu","family":"Dong","sequence":"additional","affiliation":[]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[]},{"given":"Narayanan","family":"Vijaykrishnan","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2010,11,6]]},"reference":[{"key":"11_CR1","unstructured":"Stanford University CS488a Spring 2007 Real-Time Graphics Architecture, available at: http:\/\/graphics.stanford.edu\/cs448-07-spring\/"},{"key":"11_CR2","doi-asserted-by":"crossref","unstructured":"R. del Barrio, V. M. Gonzalez, C. Roca, J. Fernandez, and A. Espasa E., \u201cATTILA: A Cycle-Level Execution-Driven Simulator for Modern GPU Architectures,\u201d in Proc. International Symposium on Performance Analysis of Systems and Software, 2006, pages 231\u2013241","DOI":"10.1109\/ISPASS.2006.1620807"},{"key":"11_CR3","unstructured":"General-Purpose Computation Using Graphics Hardware, available at: www.gpgpu.com"},{"key":"11_CR4","unstructured":"Nvidia: CUDA Homepage, available at: http:\/\/www.nvidia.com\/object\/cuda_home.html"},{"key":"11_CR5","unstructured":"ATI Stream Software Development Kit (SDK), available at: http:\/\/developer.amd.com\/gpu\/ATIStreamSDK\/Pages\/default.aspx"},{"key":"11_CR6","unstructured":"GeForce GTX200 Technical Brief, available at: http:\/\/www.nvidia.com\/docs\/IO\/55506\/GeForce_GTX_200_GPU_Technical_Brief.pdf"},{"key":"11_CR7","doi-asserted-by":"crossref","unstructured":"Yuh-Fang Tsai, Y. Xie, N. Vijaykrishnan, and M. Jane Irwin, \u201cThree-Dimensional Cache Design Exploration Using 3DCacti,\u201d in Proc. International Conference on Computer Design, 2005, pages 519\u2013524","DOI":"10.1109\/ICCD.2005.108"},{"key":"11_CR8","doi-asserted-by":"crossref","unstructured":"N. Govindaraju, S. Larsen, J. Gray, and D. Manocha, \u201cA Memory Model for Scientific Algorithms on Graphics Processors,\u201d in Proc. Conference on High Performance Networking and Computing, 2006. Article No. 89","DOI":"10.1109\/SC.2006.2"},{"key":"11_CR9","unstructured":"N. Goodnight, C. Woolley, G. Lewin, D. Luebke, and G. Humphreys, \u201cA Multigrid Solver for Boundary Value Problems Using Programmable Graphics Hardware,\u201d in Proc. SIGGRAPH\/EUROGRAPHICS Conference on Graphics Hardware, 2003, pages 102\u2013111"},{"key":"11_CR10","doi-asserted-by":"crossref","unstructured":"K. Fatahalian, J. Sugerman, and P. Hanrahan, \u201cUnderstanding the Efficiency of GPU Algorithms for Matrix-Matrix Multiplication,\u201d in Proc. SIGGRAPH, 2004, pages 133\u2013137","DOI":"10.1145\/1058129.1058148"},{"key":"11_CR11","unstructured":"CACTI Cache Simulator, available at: http:\/\/www.hpl.hp.com\/research\/cacti\/"},{"key":"11_CR12","unstructured":"V. K. Kodavalla, \u201cIP Gate Count Estimation Methodology During Micro-Architecture Phase,\u201d in IP based Electronic System Conference and Exhibition, Dec. 5\u20136 2007, Grenoble, France, available at: http:\/\/www.design-reuse.com\/ipbasedsocdesign\/slides_2007-32_01.html"},{"key":"11_CR13","unstructured":"ITRS, \u201cInternational Technology Roadmap for Semiconductors,\u201d available at: www.itrs.net"},{"key":"11_CR14","doi-asserted-by":"crossref","unstructured":"X. Dong, and Y. Xie, \u201cSystem-Level Cost Analysis and Design Exploration for 3D ICs,\u201d in Proc. Asia and South Pacific Design Automation Conference, 2009, pages 234\u2013241, Yokohama, Japan","DOI":"10.1109\/ASPDAC.2009.4796486"},{"key":"11_CR15","volume-title":"Computer Architecture: A Quantitative Approach. Fourth Edition","author":"J. L. Hennessy","year":"2010","unstructured":"J. L. Hennessy, and D. A. Patterson, Computer Architecture: A Quantitative Approach. Fourth Edition, Wiley, San Francisco, CA, 2010"},{"key":"11_CR16","unstructured":"M. Saravana Sibi Govindan, S. W. Keckler, S. R. Nassif, and E. Acar, \u201cA Temperature Aware Power Estimation Methodology,\u201d ASPDAC, January 2008"},{"issue":"2","key":"11_CR17","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1145\/871656.859620","volume":"31","author":"Kevin Skadron","year":"2003","unstructured":"K. Skadron, M. R. Stan, W. Velusamy, K. Sankaranarayanan, and D. Tarjan, \u201cTemperature-Aware Microarchitecture,\u201d in Proc. International Symposium on Computer Architecture, 2003, pages 2\u201313","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"11_CR18","unstructured":"Attila Project: AttilaWiki, available at: https:\/\/attila.ac.upc.edu\/wiki\/index.php\/Main_Page , 2008"},{"key":"11_CR19","unstructured":"OpenGL, available at: http:\/\/www.opengl.org\/"},{"key":"11_CR20","unstructured":"DirectX Library, available at: http:\/\/www.microsoft.com\/games\/ en-US\/aboutGFW\/pages\/directx.aspx"},{"issue":"2","key":"11_CR21","doi-asserted-by":"publisher","first-page":"126","DOI":"10.1109\/MC.2007.59","volume":"40","author":"D. Luebke","year":"2007","unstructured":"D. Luebke, and G. Humphreys, How GPUs Work, in IEEE Computer, vol. 40, no. 2, pages 126\u2013130, 2007","journal-title":"in IEEE Computer"},{"key":"11_CR22","unstructured":"S. Jones, \u201c2008 IC Economics Report,\u201d in IC Knowledge LLC, 2008, available at: http:\/\/www.icknowledge.com\/"},{"key":"11_CR23","doi-asserted-by":"crossref","unstructured":"S. Rodriguez, and B. Jacob, \u201cEnergy\/power Breakdown of Pipelined Nanometer Caches (90nm\/65nm\/45nm\/32),\u201d in Proc. International Symposium on Low Power Electronics and Design, 2006, pages 25\u201330","DOI":"10.1145\/1165573.1165581"},{"key":"11_CR24","unstructured":"J. D. Hall, N. Carr, and J. Hart, \u201cCache and Bandwidth Aware Matrix Multiplication on the GPU,\u201d Technical Report UIUCDCS-R-2003-2328, University of Illinois Urbana-Champain, 2003"},{"key":"11_CR25","doi-asserted-by":"crossref","unstructured":"M. Silberstein, A. Schuster, D. Geiger, A. Patney, and J. D. Owens, \u201cEfficient Computation of Sum-Products on GPUs Through Software-Managed Cache,\u201d in Proc. Inter. Conference on Supercomputing, 2008, pages 308\u2013318","DOI":"10.1145\/1375527.1375572"},{"key":"11_CR26","doi-asserted-by":"crossref","unstructured":"G. Luca Loi, B. Agrawal, N. Srivastava, Sheng-Chih Lin, T. Sherwood, and K. Banerjee, \u201cA Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy,\u201d in Proc. Design Automation Conference, 2006, pages 991\u2013996","DOI":"10.1109\/DAC.2006.229426"},{"key":"11_CR27","doi-asserted-by":"crossref","unstructured":"K. Puttaswamy, and G. H. Loh, \u201cThermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors,\u201d in Proc. HPCA, 2007, pages 193\u2013204","DOI":"10.1109\/HPCA.2007.346197"},{"key":"11_CR28","doi-asserted-by":"crossref","unstructured":"M. Hosomi, H. Yamagishi, and T. Yamamoto, \u201cA Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-Ram,\u201d in International Electron Devices Meeting, 2005, pages 459\u2013462","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"11_CR29","doi-asserted-by":"crossref","unstructured":"J. Owens, \u201cGPU Architecture Overview,\u201d in Proc. International Conference on Computer Graphics and Interactive Techniques, 2007, Article No. 2","DOI":"10.1145\/1281500.1281643"},{"key":"11_CR30","doi-asserted-by":"crossref","unstructured":"A. Al Maashri, G. Sun, X. Dong, V. Narayanan, and Y. Xie, \u201c3D GPU Architecture Using Cache Stacking: Performance, Cost, Power, and Thermal Analysis,\u201d in Proc. International Conference on Computer Design (ICCD), 2009","DOI":"10.1109\/ICCD.2009.5413147"}],"container-title":["Integrated Circuits and Systems","3D Integration for NoC-based SoC Architectures"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4419-7618-5_11","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,27]],"date-time":"2025-02-27T16:31:42Z","timestamp":1740673902000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-1-4419-7618-5_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11,6]]},"ISBN":["9781441976178","9781441976185"],"references-count":30,"URL":"https:\/\/doi.org\/10.1007\/978-1-4419-7618-5_11","relation":{},"ISSN":["1558-9412","1558-9420"],"issn-type":[{"type":"print","value":"1558-9412"},{"type":"electronic","value":"1558-9420"}],"subject":[],"published":{"date-parts":[[2010,11,6]]},"assertion":[{"value":"6 November 2010","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}