{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:56:01Z","timestamp":1725569761083},"publisher-location":"New York, NY","reference-count":48,"publisher":"Springer New York","isbn-type":[{"type":"print","value":"9781441976178"},{"type":"electronic","value":"9781441976185"}],"license":[{"start":{"date-parts":[[2010,11,6]],"date-time":"2010-11-06T00:00:00Z","timestamp":1289001600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011]]},"DOI":"10.1007\/978-1-4419-7618-5_8","type":"book-chapter","created":{"date-parts":[[2010,11,5]],"date-time":"2010-11-05T11:52:13Z","timestamp":1288957933000},"page":"167-191","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Design of Application-Specific 3D Networks-on-Chip Architectures"],"prefix":"10.1007","author":[{"given":"Shan","family":"Yan","sequence":"first","affiliation":[]},{"given":"Bill","family":"Lin","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2010,11,6]]},"reference":[{"key":"8_CR1","doi-asserted-by":"crossref","unstructured":"W. J. Dally, B. Towles, \u201cRoute packet, not wires: On-chip interconnection networks,\u201d DAC, 2001.","DOI":"10.1145\/378239.379048"},{"key":"8_CR2","doi-asserted-by":"publisher","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L. Benini","year":"2002","unstructured":"L. Benini, G. De Micheli, \u201cNetworks on chips: A new SoC paradigm,\u201d IEEE Computer, vol.\u00a035, no.\u00a01, pp.\u00a070\u201378, Jan. 2002.","journal-title":"IEEE Computer"},{"key":"8_CR3","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/MM.2002.997877","volume":"22","author":"M. B. Taylor","year":"2002","unstructured":"M. B. Taylor et al., \u201cThe RAW microprocessor: A computational fabric for software circuits and general-purpose programs,\u201d IEEE Micro, vol.\u00a022, no.\u00a06, pp.\u00a025\u201335, Mar.\/Apr. 2002.","journal-title":"IEEE Micro"},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"K. Sankaralingam et al., \u201cExploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture,\u201d ISCA, 2003.","DOI":"10.1145\/859618.859667"},{"key":"8_CR5","doi-asserted-by":"crossref","unstructured":"J. Hu, R. Marculescu, \u201cEnergy-aware mapping for tile-based NoC architectures under performance constraints,\u201d ASP-DAC, 2003.","DOI":"10.1145\/1119772.1119818"},{"key":"8_CR6","unstructured":"S. Murali, G. De Micheli, \u201cBandwidth constrained mapping of cores onto NoC architectures,\u201d DATE, 2004."},{"key":"8_CR7","doi-asserted-by":"publisher","first-page":"407","DOI":"10.1109\/TVLSI.2006.871762","volume":"14","author":"K. Srinivasan","year":"2006","unstructured":"K. Srinivasan, K. S. Chatha, G. Konjevod, \u201cLinear-programming-based techniques for synthesis of network-on-chip architectures,\u201d IEEE Transactions on VLSI Systems, vol.\u00a014, no.\u00a04, pp.\u00a0407\u2013420, Apr. 2006.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"8_CR8","doi-asserted-by":"crossref","unstructured":"S. Murali et al., \u201cDesigning application-specific networks on chips with floorplan information,\u201d ICCAD, 2006.","DOI":"10.1109\/ICCAD.2006.320058"},{"key":"8_CR9","unstructured":"S. Yan, B. Lin, \u201cApplication-specific network-on-chip architecture synthesis based on set partitions and Steiner trees,\u201d ASPDAC, 2008."},{"key":"8_CR10","unstructured":"S. Yan, B. Lin, \u201cCustom networks-on-chip architectures with multicast routing,\u201d IEEE Transactions on VLSI Systems, accepted for publication, 2008."},{"key":"8_CR11","unstructured":"K. Lee et al., \u201cThree-dimensional shared memory fabricated using wafer stacking technology,\u201d IEDM Technical Digest, Dec. 2000."},{"key":"8_CR12","doi-asserted-by":"publisher","first-page":"601","DOI":"10.1109\/TED.2003.810465","volume":"50","author":"L. Xue","year":"2003","unstructured":"L. Xue et al., \u201cThree dimensional integration: Technology, use, and issues for mixed-signal applications,\u201d IEEE Transactions on Electron Devices, vol.\u00a050, pp.\u00a0601\u2013609, May 2003.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"8_CR13","doi-asserted-by":"publisher","first-page":"498","DOI":"10.1109\/MDT.2005.136","volume":"22","author":"W. R. Davis","year":"2005","unstructured":"W. R. Davis et al., \u201cDemystifying 3D ICs: The pros and cons of going vertical,\u201d IEEE Design & Test of Computers, vol.\u00a022, no.\u00a06, pp.\u00a0498\u2013510, 2005.","journal-title":"IEEE Design & Test of Computers"},{"key":"8_CR14","doi-asserted-by":"crossref","unstructured":"M. Kawano et al., \u201cA 3D packaging technology for 4Gbit stacked DRAM with 3Gbps data transfer,\u201d IEEE International Electron Devices, pp.\u00a01\u20134, 2006.","DOI":"10.1109\/IEDM.2006.346849"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"J. Kim et al., \u201cA novel dimensionally-decomposed router for on-chip communication in 3D architectures,\u201d ISCA, 2007.","DOI":"10.1145\/1250662.1250680"},{"key":"8_CR16","doi-asserted-by":"publisher","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","volume":"15","author":"V. F. Pavlidis","year":"2007","unstructured":"V. F. Pavlidis, E. G. Friedman, \u201c3-D topologies for networks-on-chip,\u201d IEEE Transactions on VLSI Systems, vol.\u00a015, no.\u00a010, pp.\u00a01081\u20131090, Oct. 2007.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"8_CR17","doi-asserted-by":"crossref","unstructured":"H. Matsutani, M. Koibuchi, H. Amano, \u201cTightly-coupled multi-layer topologies for 3-D NoCs,\u201d ICPP, 2007.","DOI":"10.1109\/ICPP.2007.79"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"T. Kgil et al., \u201cPICOSERVER: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor,\u201d ASPLOS-XII, 2006.","DOI":"10.1145\/1168857.1168873"},{"key":"8_CR19","doi-asserted-by":"crossref","unstructured":"F. Li et al., \u201cDesign and management of 3D chip multiprocessors using network-in-memory,\u201d ISCA, 2006.","DOI":"10.1145\/1150019.1136497"},{"key":"8_CR20","unstructured":"P. Morrow et al., \u201cDesign and fabrication of 3D microprocessor,\u201d Material Research Society Symposium, 2007."},{"key":"8_CR21","doi-asserted-by":"crossref","unstructured":"W. A. Dees, Jr., P. G. Karger \u201cAutomated rip-up and reroute techniques,\u201d DAC, 1982.","DOI":"10.1109\/DAC.1982.1585535"},{"key":"8_CR22","doi-asserted-by":"publisher","first-page":"942","DOI":"10.1109\/TCAD.1987.1270336","volume":"6","author":"H. Shin","year":"1987","unstructured":"H. Shin, A. Sangiovanni-Vincentelli, \u201cA detailed router based on incremental routing modifications: Mighty,\u201d IEEE Transactions on CAD of Integrated Circuits and Systems, vol.\u00a0CAD-6, no.\u00a06, pp.\u00a0942\u2013955, Nov. 1987.","journal-title":"IEEE Transactions on CAD of Integrated Circuits and Systems"},{"key":"8_CR23","unstructured":"H. Shirota, S. Shibatani, M. Terai, \u201cA new rip-up and reroute algorithm for very large scale gate arrays,\u201d ICICC, May 1996."},{"key":"8_CR24","unstructured":"J. Cong, J. Wei, Y. Zhang, \u201cThermal-driven floorplanning algorithm for 3D ICs,\u201d ICCAD, 2004."},{"key":"8_CR25","doi-asserted-by":"crossref","unstructured":"J. Cong, Y. Zhang, \u201cThermal-driven multilevel routing for 3-D ICs,\u201d ASPDAC, 2005.","DOI":"10.1145\/1120725.1120787"},{"key":"8_CR26","unstructured":"B. Goplen, S. Sapatnekar, \u201cEfficient thermal placement of standard cells in 3D ICs using a force directed approach,\u201d ICCAD, 2003."},{"key":"8_CR27","unstructured":"M. Pathak, S. K. Lim, \u201cThermal-aware Steiner routing for 3D stacked ICs,\u201d ICCAD, 2007."},{"key":"8_CR28","unstructured":"C. Addo-Quaye, \u201cThermal-aware mapping and placement for 3-D NoC designs,\u201d IEEE International SOC Conference, 2005."},{"key":"8_CR29","doi-asserted-by":"publisher","first-page":"793","DOI":"10.1109\/71.298203","volume":"5","author":"X. Lin","year":"1994","unstructured":"X. Lin, P. K. McKinley, L. M. Ni, \u201cDeadlock-free multicast wormhole routing in 2-D mesh multicomputers,\u201d IEEE Transactions on Parallel and Distributed Systems, vol.\u00a05, no.\u00a08, pp.\u00a0793\u2013804, Aug. 1994.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"8_CR30","unstructured":"M. P. Malumbres, J. Duato, J. Torrellas, \u201cAn efficient implementation of tree-based multicast routing for distributed shared-memory,\u201d IEEE Symposium on Parallel and Distributed Processing, 1996."},{"key":"8_CR31","doi-asserted-by":"publisher","first-page":"414","DOI":"10.1109\/MDT.2005.99","volume":"22","author":"K Goossens","year":"2005","unstructured":"K. Goossens, J. Dielissen, A. Radulescu, \u201cThe Ethereal network on chip: Concepts, architectures, and implementations,\u201d IEEE Design & Test of Computers, vol.\u00a022, no.\u00a05, pp.\u00a0414\u2013421, 2005.","journal-title":"IEEE Design & Test of Computers"},{"key":"8_CR32","unstructured":"M. Millberg et al., \u201cGuaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip,\u201d DATE, 2004."},{"key":"8_CR33","unstructured":"Z. Lu, B. Yin, A. Jantsch, \u201cConnection-oriented multicasting in wormhole-switched networks on chip,\u201d Emerging VLSI Technologies and Architectures (ISVLSI), 2006."},{"key":"8_CR34","doi-asserted-by":"crossref","unstructured":"F. A. Samman, T. Hollstein, M. Glesner, \u201cMulticast parallel pipeline router architecture for network-on-chip,\u201d DATE, 2008.","DOI":"10.1109\/DATE.2008.4484869"},{"key":"8_CR35","doi-asserted-by":"crossref","unstructured":"E. A. Carara, F. G. Moraes, \u201cDeadlock-free multicast routing algorithm for wormhole-switched mesh networks-on-chip,\u201d ISVLSI, 2008.","DOI":"10.1109\/ISVLSI.2008.18"},{"key":"8_CR36","first-page":"1396","volume":"14","author":"Y. J. Chu","year":"1965","unstructured":"Y. J. Chu, T. H. Liu, \u201cOn the shortest arborescence of a directed graph,\u201d Science Sinica, vol.\u00a014, pp.\u00a01396\u20131400, 1965.","journal-title":"Science Sinica"},{"key":"8_CR37","doi-asserted-by":"publisher","first-page":"233","DOI":"10.6028\/jres.071B.032","volume":"71","author":"J. Edmonds","year":"1967","unstructured":"J. Edmonds, \u201cOptimum branchings,\u201d Research of the National Bureau of Standards, vol.\u00a071B, pp.\u00a0233\u2013240, 1967.","journal-title":"Research of the National Bureau of Standards"},{"key":"8_CR38","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1109\/TVLSI.2005.863750","volume":"14","author":"G. Chen","year":"2006","unstructured":"G. Chen, E. G. Friedman, \u201cLow-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints,\u201d IEEE Transactions on VLSI Systems, vol.\u00a014, no.\u00a02, pp.161\u2013172, Feb. 2006.","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"8_CR39","doi-asserted-by":"crossref","unstructured":"L. Zhang et al., \u201cRepeated on-chip interconnect analysis and evaluation of delay, power, and bandwidth metrics under different design goals,\u201d ISQED, 2007.","DOI":"10.1109\/ISQED.2007.139"},{"key":"8_CR40","unstructured":"The international Technology roadmap for semiconductors, 2007."},{"key":"8_CR41","unstructured":"H. Wang et al., \u201cOrion: A power-performance simulator for interconnection networks,\u201d MICRO 35, Nov. 2002."},{"key":"8_CR42","doi-asserted-by":"crossref","unstructured":"X. Chen, L.-S. Peh, \u201cLeakage power modeling and optimization in interconnection networks,\u201d ISPLED, 2003.","DOI":"10.1145\/871506.871531"},{"key":"8_CR43","doi-asserted-by":"crossref","unstructured":"K. Srinivasan, K. S. Chatha, G. Konjevod, \u201cApplication specific network-on-chip design with guaranteed quality approximation algorithms,\u201d ASPDAC 2007, Jan 2007.","DOI":"10.1109\/ASPDAC.2007.357983"},{"key":"8_CR44","doi-asserted-by":"crossref","unstructured":"E. Rijpkema et al., \u201cTrade-offs in the design of a router with both guaranteed and best-effort services for networks on chip,\u201d DATE, 2003.","DOI":"10.1049\/ip-cdt:20030830"},{"key":"8_CR45","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1109\/L-CA.2007.2","volume":"6","author":"N. Enright-Jerger","year":"2007","unstructured":"N. Enright-Jerger, M. Lipasti, L.-S. Peh, \u201cCircuit-switched coherence,\u201d IEEE Computer Architecture Letters, vol.\u00a06, no.\u00a01, pp.\u00a05\u20138, Mar. 2007.","journal-title":"IEEE Computer Architecture Letters"},{"key":"8_CR46","doi-asserted-by":"publisher","first-page":"547","DOI":"10.1109\/TC.1987.1676939","volume":"36","author":"W. J. Dally","year":"1987","unstructured":"W. J. Dally, C. L. Seitz, \u201cDeadlock-free message routing in multiprocessor interconnection networks,\u201d IEEE Transactions on Computers, vol.\u00a0C-36, no.\u00a05, pp.\u00a0547\u2013550, May 1987.","journal-title":"IEEE Transactions on Computers"},{"key":"8_CR47","doi-asserted-by":"crossref","unstructured":"D. Greenfield et al., \u201cImplications of rent\u2019s rule for NoC design and its fault-tolerance,\u201d NOCS, May 2007.","DOI":"10.1109\/NOCS.2007.26"},{"key":"8_CR48","doi-asserted-by":"publisher","first-page":"1011","DOI":"10.1109\/43.863641","volume":"19","author":"D. Stroobandt","year":"2000","unstructured":"D. Stroobandt, P. Verplaetse, J. van Campenhout, \u201cGenerating synthetic benchmark circuits for evaluating CAD tools,\u201d IEEE Transactions on CAD of Integrated Circuits and Systems, vol.\u00a019, no.\u00a09, pp.\u00a01011\u20131022, Sep. 2000.","journal-title":"IEEE Transactions on CAD of Integrated Circuits and Systems"}],"container-title":["Integrated Circuits and Systems","3D Integration for NoC-based SoC Architectures"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4419-7618-5_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,1,9]],"date-time":"2020-01-09T03:04:30Z","timestamp":1578539070000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-1-4419-7618-5_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,11,6]]},"ISBN":["9781441976178","9781441976185"],"references-count":48,"URL":"https:\/\/doi.org\/10.1007\/978-1-4419-7618-5_8","relation":{},"ISSN":["1558-9412","1558-9420"],"issn-type":[{"type":"print","value":"1558-9412"},{"type":"electronic","value":"1558-9420"}],"subject":[],"published":{"date-parts":[[2010,11,6]]},"assertion":[{"value":"6 November 2010","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}