{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T18:06:57Z","timestamp":1725732417627},"publisher-location":"New York, NY","reference-count":19,"publisher":"Springer New York","isbn-type":[{"type":"print","value":"9781461468585"},{"type":"electronic","value":"9781461468592"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-1-4614-6859-2_42","type":"book-chapter","created":{"date-parts":[[2013,6,19]],"date-time":"2013-06-19T12:35:53Z","timestamp":1371645353000},"page":"1377-1399","source":"Crossref","is-referenced-by-count":4,"title":["Mapping Decidable Signal Processing Graphs into FPGA Implementations"],"prefix":"10.1007","author":[{"given":"Roger","family":"Woods","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2013,5,10]]},"reference":[{"key":"42_CR1","unstructured":"Altera Corp.: Stratix III device handbook. Web publication downloadable from \n                  http:\/\/www.altera.com\n                  \n                 (2007)"},{"key":"42_CR2","doi-asserted-by":"crossref","unstructured":"Bringmann, O., Rosenstiel, W.: Resource sharing in hierarchical synthesis. In: International Conference on Computer Aided Design, pp. 318\u2013325 (1997)","DOI":"10.1109\/ICCAD.1997.643537"},{"key":"42_CR3","unstructured":"Hu, Y.H., Kung, S.Y.: Systolic arrays. In: S.S. Bhattacharyya, E.F. Deprettere, R.\u00a0Leupers, J.\u00a0Takala (eds.) Handbook of Signal Processing Systems, second edn. Springer (2013)"},{"key":"42_CR4","volume-title":"VLSI Array Processors","author":"S.Y. Kung","year":"1988","unstructured":"Kung, S.Y.: VLSI Array Processors. Prentice Hall Int., Englewood Cliffs, NJ (1988)"},{"key":"42_CR5","doi-asserted-by":"crossref","unstructured":"Leiserson, C., Rose, F., Saxe, J.: Optimizing synchronous circuitry by retiming. In: Proceedings of the 3rd Caltech Conference on VLSI, pp. 87\u2013116 (1983)","DOI":"10.1007\/978-3-642-95432-0_7"},{"key":"42_CR6","unstructured":"McCanny, J., Hu, Y., Ding, T., Trainor, D., Ridge, D.: Rapid design of DSP ASIC cores using hierarchical VHDL libraries. In: Thirtieth Asilomar Conference on Signals, Systems and Computers, pp. 1344\u20131348 (1996)"},{"key":"42_CR7","volume-title":"Low power optimisation of DSP core networks on FPGA for high end signal processing systems","author":"S. McKeown","year":"2006","unstructured":"McKeown, S., Fischaber, S., Woods, R., McAllister, J., Malins, E.: Low power optimisation of DSP core networks on FPGA for high end signal processing systems. In: Proceedings on International Conference on Military and Aerospace Programmable Logic Devices (2006)"},{"key":"42_CR8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-04613-5","volume-title":"Digital Signal Processing with Field Programmable Gate Arrays","author":"U. Meyer-Baese","year":"2001","unstructured":"Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays. Springer, Germany (2001)"},{"key":"42_CR9","unstructured":"Monteiro, J., Devadas, S., Ghosh, A.: Retiming sequential circuits for low power. In:\u00a0Proceedings of IEEE Int\u2019l Conf. on Computer Aided Design, pp. 398\u2013402 (1993)"},{"key":"42_CR10","volume-title":"Computer Arithmetic Systems","author":"A.R. Omondi","year":"1994","unstructured":"Omondi, A.R.: Computer Arithmetic Systems. Prentice Hall Int., New York (1994)"},{"key":"42_CR11","volume-title":"VLSI digital signal processing systems: design and implementation","author":"K.K. Parhi","year":"1999","unstructured":"Parhi, K.K.: VLSI digital signal processing systems: design and implementation. John Wiley and Sons, Inc., New York (1999)"},{"key":"42_CR12","doi-asserted-by":"crossref","unstructured":"Parhi, K.K., Chen, Y.: Signal flow graphs and data flow graphs. In: S.S. Bhattacharyya, E.F. Deprettere, R.\u00a0Leupers, J.\u00a0Takala (eds.) Handbook of Signal Processing Systems, second edn. Springer (2013)","DOI":"10.1007\/978-1-4614-6859-2_39"},{"key":"42_CR13","unstructured":"Semiconductor Industry Association: International technology roadmap for semiconductors: Design. Web publication downloadable from \n                  http:\/\/www.itrs.net\/Links\/2005ITRS\/Design2005.pdf\n                  \n                 (2005)"},{"key":"42_CR14","doi-asserted-by":"crossref","unstructured":"Ting, L., Woods, R., Cowan, C., Cork, P., Sprigings, C.: High-performance fine-grained pipelined LMS algorithm in Virtex FPGA. In: Advanced Signal Processing Algorithms, Architectures, and Implementations X: SPIE San Diego, pp. 288\u2013299 (2000)","DOI":"10.1117\/12.406507"},{"key":"42_CR15","doi-asserted-by":"publisher","first-page":"1113","DOI":"10.1109\/TVLSI.2004.833399","volume":"12","author":"R.H. Turner","year":"2004","unstructured":"Turner, R.H., Woods, R.: Highly efficient, limited range multipliers for LUT-based FPGA architectures. IEEE Trans. on VLSI Systems 12, 1113\u20131118 (2004)","journal-title":"IEEE Trans. on VLSI Systems"},{"key":"42_CR16","doi-asserted-by":"crossref","unstructured":"White, S.A.: Applications of distributed arithmetic to digital signal processing. IEEE ASSP Magazine pp. 4\u201319 (1989)","DOI":"10.1109\/53.29648"},{"key":"42_CR17","doi-asserted-by":"crossref","unstructured":"Wilton, S.J.E., Luk, W., Ang, S.S.: The impact of pipelining on energy per operation in field-programmable gate arrays. In: Proceedings of Int\u2019l conf. on Field Programmable Logic and Application, pp. 719\u2013728 (2004)","DOI":"10.1007\/978-3-540-30117-2_73"},{"key":"42_CR18","doi-asserted-by":"publisher","DOI":"10.1002\/9780470713785","volume-title":"FPGA-based Implementation of Signal Processing Systems","author":"R. Woods","year":"2008","unstructured":"Woods, R., McAllister, J., Lightbody, G., Yi, Y.: FPGA-based Implementation of Signal Processing Systems. Wiley, UK (2008)"},{"key":"42_CR19","unstructured":"Xilinx Inc.: Using look-up tables as shift registers (SRL-16) in Spartan-3 generation FPGAs. Web publication downloadable from \n                  http:\/\/www.xilinx.com\n                  \n                 (2005)"}],"container-title":["Handbook of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4614-6859-2_42","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,14]],"date-time":"2019-05-14T04:32:42Z","timestamp":1557808362000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-1-4614-6859-2_42"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9781461468585","9781461468592"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-1-4614-6859-2_42","relation":{},"subject":[],"published":{"date-parts":[[2013]]}}}