{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T06:07:25Z","timestamp":1725602845276},"publisher-location":"Boston, MA","reference-count":9,"publisher":"Springer US","isbn-type":[{"type":"print","value":"9780792394778"},{"type":"electronic","value":"9781461526988"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1994]]},"DOI":"10.1007\/978-1-4615-2698-8_14","type":"book-chapter","created":{"date-parts":[[2011,8,25]],"date-time":"2011-08-25T05:15:00Z","timestamp":1314249300000},"page":"351-371","source":"Crossref","is-referenced-by-count":1,"title":["Analysis of Multithreaded Microprocessors under Multiprogramming"],"prefix":"10.1007","author":[{"given":"David","family":"Culler","sequence":"first","affiliation":[]},{"given":"Michial","family":"Gunter","sequence":"additional","affiliation":[]},{"given":"James","family":"Lee","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"14_CR1","first-page":"104","volume-title":"Proc. of the 17th Annual Int. Symp. on Comp. Arch.","author":"A Agarwal","year":"1990","unstructured":"A. Agarwal, B. Lim, D. Kranz, and J. Kubiatowicz. APRIL: A Processor Architecture for Multiprocessing. In Proc. of the 17th Annual Int. Symp. on Comp. Arch., pages 104\u2013114, Seattle, Washington, May 1990."},{"key":"14_CR2","first-page":"225","volume-title":"Reprinted in Dataflow and Reduction Architectures","author":"Arvind","year":"1986","unstructured":"Arvind and D. E. Culler. Dataflow Architectures. In Annual Reviews in Computer Science, volume 1, pages 225\u2013253. Annual Reviews Inc., Palo Alto, CA, 1986. Reprinted in Dataflow and Reduction Architectures, S. S. Thakkar, editor, IEEE Computer Society Press, 1987."},{"key":"14_CR3","series-title":"Proc. of the 15th Int. Symp. on Comp. Arch","first-page":"443","volume-title":"MASA: a Multithreaded Processor Architecture for Parallel Symbolic Computing","author":"RH Halstead Jr.","year":"1988","unstructured":"R. H. Halstead, Jr. and T. Fujita. MASA: a Multithreaded Processor Architecture for Parallel Symbolic Computing. In Proc. of the 15th Int. Symp. on Comp. Arch., pages 443\u2013451, 1988."},{"key":"14_CR4","series-title":"Proc. of the 10th Annual Int. Symp. on Comp. Arch.","volume-title":"Performance Measurement on HEP \u2014 A Pipelined MIMD Computer","author":"HF Jordan","year":"1983","unstructured":"H. F. Jordan. Performance Measurement on HEP \u2014 A Pipelined MIMD Computer. In Proc. of the 10th Annual Int. Symp. on Comp. Arch.,Stockholm, Sweden, June 1983."},{"key":"14_CR5","first-page":"148","volume-title":"Proc. of the 17th Annual Int. Symp. on Comp. Arch.","author":"D Lenoski","year":"1990","unstructured":"D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In Proc. of the 17th Annual Int. Symp. on Comp. Arch., pages 148\u2013159, Seattle, Washington, May 1990."},{"key":"14_CR6","series-title":"Proceedings of the 2nd Annual Symp. on Par. Algorithms and Arch","volume-title":"Analysis of Multithreaded Architectures for Parallel Computing","author":"R Saavedra-Barrerra","year":"1990","unstructured":"R. Saavedra-Barrerra, D. E. Culler, and T. von Eicken. Analysis of Multithreaded Architectures for Parallel Computing. In Proceedings of the 2nd Annual Symp. on Par. Algorithms and Arch.,July 1990."},{"key":"14_CR7","volume-title":"Evaluation of a Stall Cache: An Efficient Restricted On-Chip Instruction Cache. Proceedings 25th Hawaii International Conference on System Sciences","author":"KE Schauser","year":"1992","unstructured":"K. E. Schauser, K. Asanovic, D. A. Patterson, and E. H. Frank. Evaluation of a Stall Cache: An Efficient Restricted On-Chip Instruction Cache. Proceedings 25th Hawaii International Conference on System Sciences, Jan, 1992. (also Technical Report UCB\/CSD 91\/641, Univ. of Calif., Berkeley, Computer Science Div., July 1991.)"},{"key":"14_CR8","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/SUPERC.1988.44632","volume-title":"Proc. of Supercomputing \u201888","author":"MR Thistle","year":"1988","unstructured":"M. R. Thistle and B. J. Smith. A Processor Architecture for Horizon. In Proc. of Supercomputing \u201888,pages 35\u201341, Orlando, FL, 1988."},{"key":"14_CR9","series-title":"Proc.of the 16th Int. Symp. on Comp. Arch.","first-page":"273","volume-title":"Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results","author":"W Weber","year":"1989","unstructured":"W. Weber and A. Gupta. Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results. In Proc.\n                  of the 16th Int. Symp. on Comp. Arch., pages 273\u2013280, Jerusalem, Israel, May 1989."}],"container-title":["The Kluwer International Series in Engineering and Computer Science","Multithreaded Computer Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-1-4615-2698-8_14.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T10:15:47Z","timestamp":1619864147000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-1-4615-2698-8_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994]]},"ISBN":["9780792394778","9781461526988"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-1-4615-2698-8_14","relation":{},"ISSN":["0893-3405"],"issn-type":[{"type":"print","value":"0893-3405"}],"subject":[],"published":{"date-parts":[[1994]]}}}