{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T02:53:56Z","timestamp":1743044036365,"version":"3.40.3"},"publisher-location":"Cham","reference-count":16,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030166564"},{"type":"electronic","value":"9783030166571"}],"license":[{"start":{"date-parts":[[2019,4,12]],"date-time":"2019-04-12T00:00:00Z","timestamp":1555027200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-16657-1_86","type":"book-chapter","created":{"date-parts":[[2019,4,11]],"date-time":"2019-04-11T20:04:30Z","timestamp":1555013070000},"page":"923-933","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture"],"prefix":"10.1007","author":[{"given":"Bheemappa","family":"Halavar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Basavaraj","family":"Talawar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,4,12]]},"reference":[{"key":"86_CR1","doi-asserted-by":"crossref","unstructured":"Bose, A., Ghosal, P., Mohanty, S.P.: A low latency scalable 3D NoC using BFT topology with table based uniform routing. In: 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 136\u2013141 (2014)","DOI":"10.1109\/ISVLSI.2014.51"},{"key":"86_CR2","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Design Automation Conference, Proceedings, pp. 684\u2013689. IEEE (2001)","DOI":"10.1145\/378239.379048"},{"key":"86_CR3","volume-title":"Principles and Practices of Interconnection Networks","author":"W Dally","year":"2004","unstructured":"Dally, W., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)"},{"key":"86_CR4","unstructured":"Debora, M., Max, P., Marcio, K., Luigi, C., Altamiro, S.: Performance evaluation of hierarchical NoC topologies for stacked 3D ICs. In: Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1961\u20131964, July 2015"},{"issue":"1","key":"86_CR5","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/TC.2008.142","volume":"58","author":"BS Feero","year":"2009","unstructured":"Feero, B.S., Pande, P.P.: Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans. Comput. 58(1), 32\u201345 (2009)","journal-title":"IEEE Trans. Comput."},{"key":"86_CR6","unstructured":"Grecu, C., Pande, P.P., Ivanov, A., Saleh, R.: A scalable communication-centric SoC interconnect architecture. In: International Symposium on Signals, Circuits and Systems. In: Proceedings, SCS 2003, Cat. No. 03EX720, pp. 343\u2013348 (2004)"},{"key":"86_CR7","doi-asserted-by":"crossref","unstructured":"Jiang, N., Becker, D.U., et\u00a0al.: A detailed and flexible cycle-accurate network-on-chip simulator. In: 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 86\u201396. IEEE (2013)","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"86_CR8","unstructured":"Joyner, J.W., Zarkesh-Ha, P., et\u00a0al.: A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC). In: 14th Annual IEEE International ASIC\/SOC Conference, Proceedings, pp. 147\u2013151. IEEE (2001)"},{"key":"86_CR9","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., Li, B., Peh, L.S., Samadi, K.: Orion 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: Proceedings of the conference on Design, Automation and Test in Europe, pp. 423\u2013428. European Design and Automation Association (2009)","DOI":"10.1109\/DATE.2009.5090700"},{"key":"86_CR10","doi-asserted-by":"crossref","unstructured":"Khalil, D.: Analytical model for the propagation delay of through silicon vias. In: 9th ISQED 2008, pp. 553\u2013556 (2008)","DOI":"10.1109\/ISQED.2008.4479795"},{"key":"86_CR11","doi-asserted-by":"crossref","unstructured":"Kim, D.H., Athikulwongse, K., Lim, S.K.: A study of through-silicon-via impact on the 3D stacked IC layout. In: Proceedings of the 2009 ICCAD, pp. 674\u2013680. ACM (2009)","DOI":"10.1145\/1687399.1687524"},{"key":"86_CR12","unstructured":"Kumar, S., Jantsch, A., Soininen, J.P., et\u00a0al.: A network on chip architecture and design methodology. In: Proceedings IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002, pp. 105\u2013112 (2002)"},{"issue":"10","key":"86_CR13","doi-asserted-by":"publisher","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","volume":"15","author":"VF Pavlidis","year":"2007","unstructured":"Pavlidis, V.F., Friedman, E.G.: 3D topologies for networks-on-chip. IEEE Trans. Very Large Scale Integr. Syst. 15(10), 1081\u20131090 (2007)","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"86_CR14","doi-asserted-by":"crossref","unstructured":"Rahmani, A.M., Liljeberg, P., et\u00a0al: LastZ: an ultra optimized 3D networks-on-chip architecture. In: 2011 14th Euromicro DSD, pp. 173\u2013180 (2011)","DOI":"10.1109\/DSD.2011.26"},{"key":"86_CR15","doi-asserted-by":"crossref","unstructured":"Xu, T.C., Liljeberg, P., Tenhunen, H.: A greedy heuristic approximation scheduling algorithm for 3D multicore processors, pp. 281\u2013291. Springer, Heidelberg (2012)","DOI":"10.1007\/978-3-642-29737-3_32"},{"issue":"12","key":"86_CR16","doi-asserted-by":"publisher","first-page":"1380","DOI":"10.1016\/j.mejo.2011.09.013","volume":"42","author":"A Zia","year":"2011","unstructured":"Zia, A., Kannan, S., Jonathan Chao, H., Rose, G.S.: 3D NOC for many-core processors. Microelectron. J. 42(12), 1380\u20131390 (2011)","journal-title":"Microelectron. J."}],"container-title":["Advances in Intelligent Systems and Computing","Intelligent Systems Design and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-16657-1_86","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,15]],"date-time":"2024-02-15T07:11:40Z","timestamp":1707981100000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-16657-1_86"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4,12]]},"ISBN":["9783030166564","9783030166571"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-16657-1_86","relation":{},"ISSN":["2194-5357","2194-5365"],"issn-type":[{"type":"print","value":"2194-5357"},{"type":"electronic","value":"2194-5365"}],"subject":[],"published":{"date-parts":[[2019,4,12]]},"assertion":[{"value":"12 April 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ISDA 2018","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Intelligent Systems Design and Applications","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Vellore","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 December 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"8 December 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"isda2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/www.mirlabs.net\/isda18\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}