{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T04:57:11Z","timestamp":1743051431526,"version":"3.40.3"},"publisher-location":"Cham","reference-count":19,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030172268"},{"type":"electronic","value":"9783030172275"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-17227-5_27","type":"book-chapter","created":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T19:07:34Z","timestamp":1554145654000},"page":"387-401","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0512-7487","authenticated-orcid":false,"given":"Ana","family":"Gon\u00e7alves","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1771-4934","authenticated-orcid":false,"given":"Tiago","family":"Peres","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8556-4507","authenticated-orcid":false,"given":"M\u00e1rio","family":"V\u00e9stias","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,3,29]]},"reference":[{"issue":"3","key":"27_CR1","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1145\/1816038.1815993","volume":"38","author":"S Chakradhar","year":"2010","unstructured":"Chakradhar, S., Sankaradas, M., Jakkula, V., Cadambi, S.: A dynamically configurable coprocessor for convolutional neural networks. SIGARCH Comput. Archit. News 38(3), 247\u2013257 (2010). \n                      https:\/\/doi.org\/10.1145\/1816038.1815993","journal-title":"SIGARCH Comput. Archit. News"},{"key":"27_CR2","doi-asserted-by":"publisher","unstructured":"Chen, Y., et al.: DaDianNao: a machine-learning supercomputer. In: 2014 47th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 609\u2013622, December 2014. \n                      https:\/\/doi.org\/10.1109\/MICRO.2014.58","DOI":"10.1109\/MICRO.2014.58"},{"issue":"11","key":"27_CR3","doi-asserted-by":"publisher","first-page":"41","DOI":"10.1109\/35.41400","volume":"27","author":"YL Cun","year":"1989","unstructured":"Cun, Y.L., et al.: Handwritten digit recognition: applications of neural network chips and automatic learning. IEEE Commun. Mag. 27(11), 41\u201346 (1989). \n                      https:\/\/doi.org\/10.1109\/35.41400","journal-title":"IEEE Commun. Mag."},{"issue":"11","key":"27_CR4","doi-asserted-by":"publisher","first-page":"2601","DOI":"10.1109\/TCAD.2018.2857078","volume":"37","author":"L Gong","year":"2018","unstructured":"Gong, L., Wang, C., Li, X., Chen, H., Zhou, X.: MALOC: a fully pipelined FPGA accelerator for convolutional neural networks with all layers mapped on chip. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 37(11), 2601\u20132612 (2018). \n                      https:\/\/doi.org\/10.1109\/TCAD.2018.2857078","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst."},{"issue":"1","key":"27_CR5","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/TCAD.2017.2705069","volume":"37","author":"K Guo","year":"2018","unstructured":"Guo, K., et al.: Angel-Eye: a complete design flow for mapping CNN onto embedded FPGA. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 37(1), 35\u201347 (2018). \n                      https:\/\/doi.org\/10.1109\/TCAD.2017.2705069","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst."},{"key":"27_CR6","unstructured":"Gysel, P., Motamedi, M., Ghiasi, S.: Hardware-oriented approximation of convolutional neural networks. In: Proceedings of the 4th International Conference on Learning Representations (2016)"},{"issue":"11","key":"27_CR7","doi-asserted-by":"publisher","first-page":"5784","DOI":"10.1109\/TNNLS.2018.2808319","volume":"29","author":"P Gysel","year":"2018","unstructured":"Gysel, P., Pimentel, J., Motamedi, M., Ghiasi, S.: Ristretto: a framework for empirical study of resource-efficient inference in convolutional neural networks. IEEE Trans. Neural Netw. Learn. Syst. 29(11), 5784\u20135789 (2018). \n                      https:\/\/doi.org\/10.1109\/TNNLS.2018.2808319","journal-title":"IEEE Trans. Neural Netw. Learn. Syst."},{"key":"27_CR8","doi-asserted-by":"publisher","unstructured":"He, K., Zhang, X., Ren, S., Sun, J.: Deep residual learning for image recognition. In: 2016 IEEE Conference on Computer Vision and Pattern Recognition, CVPR, pp. 770\u2013778, June 2016. \n                      https:\/\/doi.org\/10.1109\/CVPR.2016.90","DOI":"10.1109\/CVPR.2016.90"},{"key":"27_CR9","doi-asserted-by":"crossref","unstructured":"Jia, Y., et al.: Caffe: convolutional architecture for fast feature embedding. arXiv preprint \n                      arXiv:1408.5093\n                      \n                     (2014)","DOI":"10.1145\/2647868.2654889"},{"key":"27_CR10","unstructured":"Krizhevsky, A., Sutskever, I., Hinton, G.E.: ImageNet classification with deep convolutional neural networks. In: Proceedings of the 25th International Conference on Neural Information Processing Systems, NIPS 2012, vol. 1, pp. 1097\u20131105. Curran Associates Inc., USA (2012)"},{"key":"27_CR11","doi-asserted-by":"publisher","unstructured":"Ma, Y., Suda, N., Cao, Y., Seo, J., Vrudhula, S.: Scalable and modularized RTL compilation of convolutional neural networks onto FPGA. In: 2016 26th International Conference on Field Programmable Logic and Applications, FPL, pp. 1\u20138, August 2016. \n                      https:\/\/doi.org\/10.1109\/FPL.2016.7577356","DOI":"10.1109\/FPL.2016.7577356"},{"key":"27_CR12","unstructured":"Simonyan, K., Zisserman, A.: Very deep convolutional networks for large-scale image recognition. In: Proceedings of the 3rd International Conference on Learning Representations (2015)"},{"key":"27_CR13","doi-asserted-by":"publisher","unstructured":"Szegedy, C., et al.: Going deeper with convolutions. In: 2015 IEEE Conference on Computer Vision and Pattern Recognition, CVPR, pp. 1\u20139, June 2015. \n                      https:\/\/doi.org\/10.1109\/CVPR.2015.7298594","DOI":"10.1109\/CVPR.2015.7298594"},{"issue":"2","key":"27_CR14","doi-asserted-by":"publisher","first-page":"326","DOI":"10.1109\/TNNLS.2018.2844093","volume":"30","author":"Stylianos I. Venieris","year":"2019","unstructured":"Venieris, S.I., Bouganis, C.: fpgaConvNet: mapping regular and irregular convolutional neural networks on FPGAs. IEEE Trans. Neural Netw. Learn. Syst. 1\u201317 (2018). \n                      https:\/\/doi.org\/10.1109\/TNNLS.2018.2844093","journal-title":"IEEE Transactions on Neural Networks and Learning Systems"},{"key":"27_CR15","doi-asserted-by":"publisher","unstructured":"V\u00e9stias, M., Duarte, R.P., de Sousa, J.T., Neto, H.: Parallel dot-products for deep learning on FPGA. In: 2017 27th International Conference on Field Programmable Logic and Applications, FPL, pp. 1\u20134, September 2017. \n                      https:\/\/doi.org\/10.23919\/FPL.2017.8056863","DOI":"10.23919\/FPL.2017.8056863"},{"key":"27_CR16","doi-asserted-by":"crossref","unstructured":"V\u00e9stias, M., Duarte, R.P., de Sousa, J.T., Neto, H.: Lite-CNN: a high-performance architecture to execute CNNs in low density FPGAs. In: Proceedings of the 28th International Conference on Field Programmable Logic and Applications (2018)","DOI":"10.1109\/FPL.2018.00075"},{"key":"27_CR17","doi-asserted-by":"crossref","unstructured":"Wang, J., Lou, Q., Zhang, X., Zhu, C., Lin, Y., Chen., D.: A design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA. In: 28th International Conference on Field-Programmable Logic and Applications (2018)","DOI":"10.1109\/FPL.2018.00035"},{"key":"27_CR18","doi-asserted-by":"publisher","unstructured":"Wang, Y., Xu, J., Han, Y., Li, H., Li, X.: DeepBurning: automatic generation of fpga-based learning accelerators for the neural network family. In: 2016 53rd ACM\/EDAC\/IEEE Design Automation Conference, DAC, pp. 1\u20136, June 2016. \n                      https:\/\/doi.org\/10.1145\/2897937.2898002","DOI":"10.1145\/2897937.2898002"},{"key":"27_CR19","doi-asserted-by":"publisher","unstructured":"Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., Cong, J.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2015, pp. 161\u2013170. ACM, New York (2015). \n                      https:\/\/doi.org\/10.1145\/2684746.2689060","DOI":"10.1145\/2684746.2689060"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-17227-5_27","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T09:44:14Z","timestamp":1558345454000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-17227-5_27"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030172268","9783030172275"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-17227-5_27","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"29 March 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Applied Reconfigurable Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Darmstadt","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 April 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 April 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"15","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arc2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/www.arc2019.tu-darmstadt.de\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"52","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"20","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"7","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"38% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"4.5","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"4","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information"}}]}}