{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,20]],"date-time":"2024-09-20T16:34:12Z","timestamp":1726850052961},"publisher-location":"Cham","reference-count":57,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030222765"},{"type":"electronic","value":"9783030222772"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-22277-2_12","type":"book-chapter","created":{"date-parts":[[2019,12,31]],"date-time":"2019-12-31T07:02:28Z","timestamp":1577775748000},"page":"295-311","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["SOI FinFET for Computer Networks and Cyber Security Systems"],"prefix":"10.1007","author":[{"given":"Neeraj","family":"Jain","sequence":"first","affiliation":[]},{"given":"Balwinder","family":"Raj","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,1,1]]},"reference":[{"key":"12_CR1","doi-asserted-by":"publisher","first-page":"2320","DOI":"10.1109\/16.887014","volume":"47","author":"D Hisamoto","year":"2000","unstructured":"Hisamoto, D., Lee, W. C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., et al. (2000). FinFET-A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47, 2320\u20132325.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR2","doi-asserted-by":"publisher","DOI":"10.4018\/978-1-5225-0105-3","volume-title":"Handbook of research on modern cryptographic solutions for computer and cyber security","author":"B Gupta","year":"2016","unstructured":"Gupta, B., Agrawal, D. P., & Yamaguchi, S. (2016). Handbook of research on modern cryptographic solutions for computer and cyber security. Hershey, PA: IGI Global."},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Ab Malek, M. S. B., Ahmadon, M. A. B., Yamaguchi, S., & Gupta, B. B. (2016). On privacy verification in the IoT service based on PN 2. In Consumer Electronics 2016 IEEE 5th Global Conference, IEEE (pp. 1\u20134).","DOI":"10.1109\/GCCE.2016.7800314"},{"key":"12_CR4","doi-asserted-by":"publisher","first-page":"619","DOI":"10.1016\/j.future.2017.04.039","volume":"83","author":"VA Memos","year":"2017","unstructured":"Memos, V. A., Psannis, K. E., Ishibashi, Y., Kim, B.-G., & Gupta, B. B. (2017). An efficient algorithm for media-based surveillance system (EAMSuS) in IoT Smart City framework. Future Generation Computer Systems, 83, 619\u2013628.","journal-title":"Future Generation Computer Systems"},{"key":"12_CR5","doi-asserted-by":"publisher","first-page":"1085","DOI":"10.1007\/s11227-016-1849-x","volume":"73","author":"A Tewari","year":"2017","unstructured":"Tewari, A., & Gupta, B. B. (2017). Cryptanalysis of a novel ultra-lightweight mutual authentication protocol for IoT devices using RFID tags. Journal of Supercomputing, 73, 1085\u20131102.","journal-title":"Journal of Supercomputing"},{"key":"12_CR6","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1016\/j.future.2015.09.031","volume":"57","author":"V Chang","year":"2016","unstructured":"Chang, V., Kuo, Y.-H., & Ramachandran, M. (2016). Cloud computing adoption framework: A security framework for business clouds. Future Generation Computer Systems, 57, 24\u201341.","journal-title":"Future Generation Computer Systems"},{"key":"12_CR7","doi-asserted-by":"publisher","first-page":"3371","DOI":"10.1109\/TED.2013.2278201","volume":"60","author":"PK Pal","year":"2013","unstructured":"Pal, P. K., Kaushik, B. K., & Dasgupta, S. (2013). High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs. IEEE Transactions on Electron Devices, 60, 3371\u20133377.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR8","doi-asserted-by":"publisher","first-page":"3579","DOI":"10.1109\/TED.2014.2351616","volume":"61","author":"PK Pal","year":"2014","unstructured":"Pal, P. K., Kaushik, B. K., & Dasgupta, S. (2014). Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective. IEEE Transactions on Electron Devices, 61, 3579\u20133585.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR9","series-title":"Handbook of research on computational simulation and modeling in engineering","first-page":"640","volume-title":"Simulations and modeling of TFET for low power design","author":"S Kumar","year":"2016","unstructured":"Kumar, S., & Raj, B. (2016). Simulations and modeling of TFET for low power design (Handbook of research on computational simulation and modeling in engineering) (pp. 640\u2013667). Hershey, PA: IGI Global."},{"key":"12_CR10","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1109\/MCD.2004.1263404","volume":"20","author":"EJ Nowak","year":"2004","unstructured":"Nowak, E. J., Aller, I., Ludwig, T., Kim, K., Joshi, R. V., Chuang, C.-T., et al. (2004). Turning silicon on its edge [double gate CMOS\/FinFET technology]. IEEE Circuits and Devices Magazine, 20, 20\u201331.","journal-title":"IEEE Circuits and Devices Magazine"},{"key":"12_CR11","doi-asserted-by":"publisher","first-page":"139","DOI":"10.1109\/LED.2006.889239","volume":"28","author":"A Kranti","year":"2007","unstructured":"Kranti, A., & Armstrong, G. A. (2007). Source\/drain extension region engineering in FinFETs for low-voltage analog applications. IEEE Electron Device Letters, 28, 139\u2013141.","journal-title":"IEEE Electron Device Letters"},{"key":"12_CR12","doi-asserted-by":"publisher","first-page":"2410","DOI":"10.1109\/TED.2010.2057195","volume":"57","author":"HG Virani","year":"2010","unstructured":"Virani, H. G., Adari, R. B. R., & Kottantharayil, A. (2010). Dual-k spacer device architecture for the improvement of performance of silicon n-channel tunnel FETs. IEEE Transactions on Electron Devices, 57, 2410\u20132417.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR13","doi-asserted-by":"publisher","first-page":"820","DOI":"10.1007\/s10825-015-0718-9","volume":"14","author":"S Kumar","year":"2015","unstructured":"Kumar, S., & Raj, B. (2015). Compact channel potential analytical modeling of DG-TFET based on evanescent-mode approach. Journal of Computational Electronics, 14, 820\u2013827.","journal-title":"Journal of Computational Electronics"},{"key":"12_CR14","doi-asserted-by":"publisher","first-page":"045004","DOI":"10.1088\/0268-1242\/27\/4\/045004","volume":"27","author":"GC Patil","year":"2012","unstructured":"Patil, G. C., & Qureshi, S. (2012). Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits. Semiconductor Science and Technology, 27, 045004.","journal-title":"Semiconductor Science and Technology"},{"key":"12_CR15","doi-asserted-by":"publisher","first-page":"883","DOI":"10.1016\/j.mejo.2012.06.001","volume":"43","author":"A Nandi","year":"2012","unstructured":"Nandi, A., Saxena, A. K., & Dasgupta, S. (2012). Impact of dual-k spacer on analog performance of underlap FinFET. Microelectronics Journal, 43, 883\u2013887.","journal-title":"Microelectronics Journal"},{"key":"12_CR16","doi-asserted-by":"publisher","first-page":"1105","DOI":"10.1109\/TED.2015.2400053","volume":"62","author":"PK Pal","year":"2015","unstructured":"Pal, P. K., Kaushik, B. K., & Dasgupta, S. (2015). Asymmetric dual-spacer trigate FinFET device-circuit codesign and its variability analysis. IEEE Transactions on Electron Devices, 62, 1105\u20131112.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR17","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1166\/rase.2016.1113","volume":"5","author":"N Jain","year":"2016","unstructured":"Jain, N., & Raj, B. (2016). An analog and digital design perspective comprehensive approach on Fin-FET (fin-field effect transistor) technology\u2014A review. Reviews in Advanced Sciences and Engineering, 5, 123\u2013137.","journal-title":"Reviews in Advanced Sciences and Engineering"},{"key":"12_CR18","doi-asserted-by":"publisher","first-page":"296","DOI":"10.1109\/TED.2010.2090421","volume":"58","author":"A Goel","year":"2011","unstructured":"Goel, A., Gupta, S. K., & Roy, K. (2011). Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Transactions on Electron Devices, 58, 296\u2013308.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR19","doi-asserted-by":"publisher","first-page":"323","DOI":"10.1166\/jno.2016.1902","volume":"11","author":"S Kumar","year":"2016","unstructured":"Kumar, S., & Raj, B. (2016). Analysis of I ON and Ambipolar current for dual-material gate-drain overlapped DG-TFET. Journal of Nanoelectronics and Optoelectronics, 11, 323\u2013333.","journal-title":"Journal of Nanoelectronics and Optoelectronics"},{"key":"12_CR20","doi-asserted-by":"publisher","first-page":"2787","DOI":"10.1016\/j.comnet.2010.05.010","volume":"54","author":"L Atzori","year":"2010","unstructured":"Atzori, L., Iera, A., & Morabito, G. (2010). The internet of things: A survey. Computer Networks, 54, 2787\u20132805.","journal-title":"Computer Networks"},{"key":"12_CR21","volume-title":"Nanoelectronic mixed-signal system design","author":"SP Mohanty","year":"2015","unstructured":"Mohanty, S. P. (2015). Nanoelectronic mixed-signal system design. New York: McGraw-Hill Education."},{"key":"12_CR22","first-page":"1864","volume":"19","author":"A Jain","year":"2016","unstructured":"Jain, A., Sharma, S., & Raj, B. (2016). Design and analysis of high sensitivity photosensor using cylindrical surrounding gate MOSFET for low power sensor applications. Engineering Science and Technology, 19, 1864\u20131870.","journal-title":"Engineering Science and Technology"},{"key":"12_CR23","unstructured":"Kumar, S., & Raj, B. Simulation of nanoscale TFET device structure for low power applications. In Proceedings of International Conference on Electrical Electronics and Industrial Automation held on 23rd--24th January 2016. Pattaya, Thailand. ISBN: 9788193137338."},{"key":"12_CR24","doi-asserted-by":"publisher","first-page":"762","DOI":"10.1166\/qm.2016.1381","volume":"5","author":"S Kumar","year":"2016","unstructured":"Kumar, S., Kumar, S., Karamveer, Kumar, K., & Raj, B. (2016). Analysis of double gate dual material TFET device for low power SRAM cell design. Quantum Matter, 5, 762\u2013766.","journal-title":"Quantum Matter"},{"key":"12_CR25","doi-asserted-by":"publisher","first-page":"423","DOI":"10.1007\/s11235-017-0345-9","volume":"67","author":"V Adat","year":"2018","unstructured":"Adat, V., & Gupta, B. B. (2018). Security in internet of things: Issues, challenges, taxonomy, and architecture. Telecommunication Systems, 67, 423\u2013441.","journal-title":"Telecommunication Systems"},{"key":"12_CR26","doi-asserted-by":"publisher","first-page":"964","DOI":"10.1016\/j.future.2016.11.031","volume":"78","author":"C Stergiou","year":"2018","unstructured":"Stergiou, C., Psannis, K. E., Kim, B.-G., & Gupta, B. (2018). Secure integration of IoT and cloud computing. Future Generation Computer Systems, 78, 964\u2013975.","journal-title":"Future Generation Computer Systems"},{"key":"12_CR27","first-page":"194","volume":"113","author":"N Jain","year":"2018","unstructured":"Jain, N., & Raj, B. (2018). Capacitance\/resistance modeling and analog performance evaluation of 3-D SOI FinFET structure for circuit perspective applications. World Scientific News, 113, 194\u2013209.","journal-title":"World Scientific News"},{"key":"12_CR28","doi-asserted-by":"crossref","unstructured":"Kumar, S., & Raj, B. (2015). Modeling of DG-tunnel FET for low power VLSI circuit design. In 2015 Eighth International Conference on Contemporary Computing, IEEE (pp. 455\u2013458).","DOI":"10.1109\/IC3.2015.7346724"},{"key":"12_CR29","volume-title":"Computer and cyber security: Principles, algorithm, applications, and perspectives","author":"BB Gupta","year":"2018","unstructured":"Gupta, B. B. (2018). Computer and cyber security: Principles, algorithm, applications, and perspectives. Boca Raton, FL: CRC Press."},{"key":"12_CR30","doi-asserted-by":"publisher","first-page":"143","DOI":"10.4018\/IJCAC.2018010107","volume":"8","author":"H Ko","year":"2018","unstructured":"Ko, H., Mesicek, L., Choi, J., Choi, J., & Hwang, S. (2018). A study on secure contents strategies for applications with DRM on cloud computing. International Journal of Cloud Applications and Computing, 8, 143\u2013153.","journal-title":"International Journal of Cloud Applications and Computing"},{"key":"12_CR31","doi-asserted-by":"publisher","first-page":"1402","DOI":"10.1109\/JIOT.2018.2844727","volume":"6","author":"L Wang","year":"2019","unstructured":"Wang, L., Li, L., Li, J., Li, J., Gupta, B. B., & Liu, X. (2019). Compressive sensing of medical images with confidentially homomorphic aggregations. IEEE Internet Things Journal, 6, 1402\u20131409.","journal-title":"IEEE Internet Things Journal"},{"key":"12_CR32","doi-asserted-by":"publisher","first-page":"134","DOI":"10.1016\/j.spmi.2014.11.037","volume":"78","author":"SK Mohapatra","year":"2015","unstructured":"Mohapatra, S. K., Pradhan, K. P., & Sahu, P. K. (2015). Temperature dependence inflection point in ultra-thin Si directly on insulator (SDOI) MOSFETs: An influence to key performance metrics. Superlattices and Microstructures, 78, 134\u2013143.","journal-title":"Superlattices and Microstructures"},{"key":"12_CR33","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1016\/j.sbsr.2018.02.001","volume":"18","author":"S Singh","year":"2018","unstructured":"Singh, S., Raj, B., & Vishvakarma, S. K. (2018). Analytical modeling of split-gate junction-less transistor for a biosensor application. Sensing and Bio-Sensing Research, 18, 31\u201336.","journal-title":"Sensing and Bio-Sensing Research"},{"key":"12_CR34","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1016\/j.mssp.2014.11.036","volume":"31","author":"PK Sahu","year":"2015","unstructured":"Sahu, P. K., Mohapatra, S. K., & Pradhan, K. P. (2015). Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges. Materials Science in Semiconductor Processing, 31, 175\u2013183.","journal-title":"Materials Science in Semiconductor Processing"},{"key":"12_CR35","doi-asserted-by":"publisher","first-page":"1374","DOI":"10.1109\/LED.2009.2034117","volume":"30","author":"P Magnone","year":"2009","unstructured":"Magnone, P., Mercha, A., Subramanian, V., Parvais, P., Collaert, N., Dehan, M., et al. (2009). Matching performance of FinFET devices with fin widths down to 10 nm. IEEE Electron Device Letters, 30, 1374.","journal-title":"IEEE Electron Device Letters"},{"key":"12_CR36","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1016\/j.mejo.2016.04.002","volume":"53","author":"SK Sharma","year":"2016","unstructured":"Sharma, S. K., Raj, B., & Khosla, M. (2016). A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects. Microelectronics Journal, 53, 65\u201372.","journal-title":"Microelectronics Journal"},{"key":"12_CR37","doi-asserted-by":"crossref","unstructured":"Pradhan, K. P., Sahu, P. K., & Mohapatra, S. K. (2015). Analysis of symmetric high-k spacer (SHS) trigate wavy FinFET: A novel device. In India Conference (INDICON), 2015 Annual IEEE, IEEE (pp. 1\u20133).","DOI":"10.1109\/INDICON.2015.7443750"},{"key":"12_CR38","doi-asserted-by":"publisher","first-page":"169","DOI":"10.1147\/rd.462.0169","volume":"46","author":"EJ Nowak","year":"2002","unstructured":"Nowak, E. J. (2002). Maintaining the benefits of CMOS scaling when scaling bogs down. IBM Journal of Research and Development, 46, 169\u2013180.","journal-title":"IBM Journal of Research and Development"},{"key":"12_CR39","doi-asserted-by":"publisher","first-page":"56","DOI":"10.1109\/TED.2004.841333","volume":"52","author":"V Trivedi","year":"2005","unstructured":"Trivedi, V., Fossum, J. G., & Chowdhury, M. M. (2005). Nanoscale FinFETs with gate-source\/drain underlap. IEEE Transactions on Electron Devices, 52, 56\u201362.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR40","doi-asserted-by":"publisher","first-page":"63","DOI":"10.1109\/TED.2012.2226724","volume":"60","author":"K Koley","year":"2013","unstructured":"Koley, K., Dutta, A., Syamal, B., Saha, S. K., & Sarkar, C. K. (2013). Subthreshold analog\/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications. IEEE Transactions on Electron Devices, 60, 63\u201369.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR41","doi-asserted-by":"publisher","first-page":"128","DOI":"10.1109\/LED.2007.911974","volume":"29","author":"AB Sachid","year":"2008","unstructured":"Sachid, A. B., Manoj, C. R., Sharma, D. K., & Rao, V. R. (2008). Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization. IEEE Electron Device Letters, 29, 128\u2013130.","journal-title":"IEEE Electron Device Letters"},{"key":"12_CR42","doi-asserted-by":"crossref","unstructured":"Goel, A., Gupta, S., Bansal, A., Chiang, M.-H., & Roy, K. (2009). Double-gate MOSFETs with asymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM. In 2009 Device Res Conf., IEEE (pp. 57\u201358).","DOI":"10.1109\/DRC.2009.5354884"},{"key":"12_CR43","unstructured":"Sentaurus TCAD user\u2019s manual. (2009). Synopsys Sentaurus Device (pp. 191\u2013413). Retrieved from \nhttp:\/\/www.synopsys.com\/"},{"key":"12_CR44","doi-asserted-by":"publisher","first-page":"546","DOI":"10.1109\/TNANO.2015.2415555","volume":"14","author":"SK Mohapatra","year":"2015","unstructured":"Mohapatra, S. K., Pradhan, K. P., Singh, D., & Sahu, P. K. (2015). The role of geometry parameters and fin aspect ratio of sub-20nm SOI-FinFET: An analysis towards analog and RF circuit design. IEEE Transactions on Nanotechnology, 14, 546\u2013554.","journal-title":"IEEE Transactions on Nanotechnology"},{"key":"12_CR45","doi-asserted-by":"publisher","first-page":"122002","DOI":"10.1088\/1674-4926\/38\/12\/122002","volume":"38","author":"N Jain","year":"2017","unstructured":"Jain, N., & Raj, B. (2017). Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length. Journal of Semiconductors, 38, 122002.","journal-title":"Journal of Semiconductors"},{"key":"12_CR46","doi-asserted-by":"publisher","first-page":"124002","DOI":"10.1088\/1674-4926\/39\/12\/124002","volume":"39","author":"N Jain","year":"2018","unstructured":"Jain, N., & Raj, B. (2018). Analysis and performance exploration of high performance (HfO2) SOI FinFETs over the conventional (Si3 N4) SOI FinFET towards analog\/RF design. Journal of Semiconductors, 39, 124002.","journal-title":"Journal of Semiconductors"},{"key":"12_CR47","doi-asserted-by":"publisher","first-page":"144","DOI":"10.1016\/j.mejo.2013.11.016","volume":"45","author":"KP Pradhan","year":"2014","unstructured":"Pradhan, K. P., Mohapatra, S. K., Sahu, P. K., & Behera, D. K. (2014). Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectronics Journal, 45, 144\u2013151.","journal-title":"Microelectronics Journal"},{"key":"12_CR48","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/TED.2012.2224870","volume":"60","author":"B Ho","year":"2013","unstructured":"Ho, B., Sun, X., Shin, C., & Liu, T. J. K. (2013). Design optimization of multigate bulk MOSFETs. IEEE Transactions on Electron Devices, 60, 28\u201333.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR49","doi-asserted-by":"publisher","first-page":"63","DOI":"10.1016\/j.sse.2011.10.022","volume":"71","author":"MGC Andrade De","year":"2012","unstructured":"De Andrade, M. G. C., Martino, J. A., Aoulaiche, M., Collaert, N., Simoen, E., & Claeys, C. (2012). Behavior of triple-gate bulk FinFETs with and without DTMOS operation. Solid State Electronics, 71, 63\u201368.","journal-title":"Solid State Electronics"},{"key":"12_CR50","unstructured":"ITRS. (2013). International technology roadmap for semiconductors 2013; Executive summary. ITRS [internet], 80. Retrieved from \nhttp:\/\/www.itrs.net\/ITRS"},{"key":"12_CR51","doi-asserted-by":"publisher","first-page":"1045","DOI":"10.1109\/T-ED.1975.18267","volume":"22","author":"C Canali","year":"1975","unstructured":"Canali, C., Majni, G., Minder, R., & Ottaviani, G. (1975). Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature. IEEE Transactions on Electron Devices, 22, 1045\u20131047.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"12_CR52","doi-asserted-by":"publisher","first-page":"1164","DOI":"10.1109\/43.9186","volume":"7","author":"C Lombardi","year":"1988","unstructured":"Lombardi, C., Manzini, S., Saporito, A., & Vanzi, M. (1988). A physically based mobility model for numerical simulation of nonplanar devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7, 1164\u20131171. Retrieved from \nhttp:\/\/ieeexplore.ieee.org\/lpdocs\/epic03\/wrapper.htm?arnumber=9186\n\n.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"12_CR53","doi-asserted-by":"publisher","first-page":"835","DOI":"10.1103\/PhysRev.87.835","volume":"87","author":"W Shockley","year":"1952","unstructured":"Shockley, W., & Read, W. T. (1952). Statistics of the recombination of holes and electrons. Physics Review, 87, 835\u2013842.","journal-title":"Physics Review"},{"key":"12_CR54","doi-asserted-by":"publisher","first-page":"387","DOI":"10.1103\/PhysRev.87.387","volume":"87","author":"RN Hall","year":"1952","unstructured":"Hall, R. N. (1952). Electron-hole recombination in germanium. Physics Review, 87, 387.","journal-title":"Physics Review"},{"key":"12_CR55","unstructured":"Sze, S. M., & Ng, K. K. (2007). Physics of semiconductor devices (3rd ed., pp. 164, 682). New York: John Wiley Sons, Inc. Retrieved from \nhttp:\/\/www.wiley.com\/WileyCDA\/WileyTitle\/productCd-0471143235.html"},{"key":"12_CR56","doi-asserted-by":"publisher","first-page":"366","DOI":"10.1002\/mop.10920","volume":"37","author":"TH Tan","year":"2003","unstructured":"Tan, T. H., & Goel, A. K. (2003). Zero-temperature-coefficient biasing point of a fully-depleted SOI MOSFET. Microwave and Optical Technology Letters, 37, 366\u2013370.","journal-title":"Microwave and Optical Technology Letters"},{"key":"12_CR57","doi-asserted-by":"publisher","first-page":"329","DOI":"10.1109\/55.57923","volume":"11","author":"G Groeseneken","year":"1990","unstructured":"Groeseneken, G., Colinge, J. P., Maes, H. E., Alderman, J. C., & Holt, S. (1990). Temperature dependence of threshold voltage in thin-film SOI MOSFET\u2019s. IEEE Electron Device Letters, 11, 329\u2013331.","journal-title":"IEEE Electron Device Letters"}],"container-title":["Handbook of Computer Networks and Cyber Security"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-22277-2_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,12,31]],"date-time":"2019-12-31T07:04:44Z","timestamp":1577775884000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-22277-2_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030222765","9783030222772"],"references-count":57,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-22277-2_12","relation":{},"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"1 January 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}