{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T14:49:45Z","timestamp":1743086985582,"version":"3.40.3"},"publisher-location":"Cham","reference-count":18,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030234249"},{"type":"electronic","value":"9783030234256"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-23425-6_1","type":"book-chapter","created":{"date-parts":[[2019,6,25]],"date-time":"2019-06-25T14:05:11Z","timestamp":1561471511000},"page":"1-13","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 65\u00a0nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load"],"prefix":"10.1007","author":[{"given":"Naoki","family":"Ojima","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Toru","family":"Nakura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tetsuya","family":"Iizuka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kunihiro","family":"Asada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,6,26]]},"reference":[{"issue":"4","key":"1_CR1","doi-asserted-by":"publisher","first-page":"933","DOI":"10.1109\/JSSC.2004.842831","volume":"40","author":"P Hazucha","year":"2005","unstructured":"Hazucha, P., Karnik, T., Bloechel, B.A., Parsons, C., Finan, D., Borkar, S.: Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits 40(4), 933\u2013940 (2005)","journal-title":"IEEE J. Solid State Circuits"},{"key":"1_CR2","doi-asserted-by":"crossref","unstructured":"Lam, Y.H., Ki, W.H.: A 0.9\u00a0V 0.35\u00a0$$\\upmu $$m adaptively biased CMOS LDO regulator with fast transient response. In: Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 442\u2013626, February 2008","DOI":"10.1109\/ISSCC.2008.4523247"},{"issue":"9","key":"1_CR3","doi-asserted-by":"publisher","first-page":"1879","DOI":"10.1109\/TCSI.2007.902615","volume":"54","author":"RJ Milliken","year":"2007","unstructured":"Milliken, R.J., Silva-Martinez, J., Sanchez-Sinencio, E.: Full on-chip CMOS low-dropout voltage regulator. IEEE Trans. Circuits Syst. I Regul. Pap. 54(9), 1879\u20131890 (2007)","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"issue":"3","key":"1_CR4","doi-asserted-by":"publisher","first-page":"565","DOI":"10.1109\/JSSC.2009.2039685","volume":"45","author":"M El-Nozahi","year":"2010","unstructured":"El-Nozahi, M., Amer, A., Torres, J., Entesari, K., Sanchez-Sinencio, E.: High PSR low drop-out regulator with feed-forward ripple cancellation technique. IEEE J. Solid State Circuits 45(3), 565\u2013577 (2010)","journal-title":"IEEE J. Solid State Circuits"},{"key":"1_CR5","unstructured":"Okuma, Y., et al.: 0.5-$${\\rm V}$$ input digital LDO with 98.7% current efficiency and 2.7-$$\\upmu $$A quiescent current in 65 nm CMOS. In: Proceedings of IEEE Custom Integrated Circuits Conference, pp. 1\u20134, September 2010"},{"issue":"11","key":"1_CR6","doi-asserted-by":"publisher","first-page":"2684","DOI":"10.1109\/JSSC.2014.2353798","volume":"49","author":"S Gangopadhyay","year":"2014","unstructured":"Gangopadhyay, S., Somasekhar, D., Tschanz, J.W., Raychowdhury, A.: A 32\u00a0nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. IEEE J. Solid State Circuits 49(11), 2684\u20132693 (2014)","journal-title":"IEEE J. Solid State Circuits"},{"key":"1_CR7","doi-asserted-by":"crossref","unstructured":"Otsuga, K., et al.: An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. In: Proceedings of IEEE International SOC Conference, pp. 11\u201314, September 2012","DOI":"10.1109\/SOCC.2012.6398369"},{"issue":"7","key":"1_CR8","doi-asserted-by":"publisher","first-page":"1281","DOI":"10.1109\/TVLSI.2014.2333755","volume":"23","author":"T Oh","year":"2015","unstructured":"Oh, T., Hwang, I.: A 110-nm CMOS 0.7-V input transient-enhanced digital low-dropout regulator with 99.98% current efficiency at 80-mA load. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(7), 1281\u20131286 (2015)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"12","key":"1_CR9","first-page":"8293","volume":"31","author":"SB Nasir","year":"2016","unstructured":"Nasir, S.B., Gangopadhyay, S., Raychowdhury, A.: All-digital low-dropout regulator with adaptive control and reduced dynamic stability for digital load circuits. IEEE Trans. Power Electron. 31(12), 8293\u20138302 (2016)","journal-title":"IEEE Trans. Power Electron."},{"issue":"11","key":"1_CR10","doi-asserted-by":"publisher","first-page":"3071","DOI":"10.1109\/JSSC.2017.2740269","volume":"52","author":"D Kim","year":"2017","unstructured":"Kim, D., Seok, M.: A fully integrated digital low-dropout regulator based on event-driven explicit time-coding architecture. IEEE J. Solid State Circuits 52(11), 3071\u20133080 (2017)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"1","key":"1_CR11","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/JSSC.2017.2766215","volume":"53","author":"LG Salem","year":"2018","unstructured":"Salem, L.G., Warchall, J., Mercier, P.P.: A successive approximation recursive digital low-dropout voltage regulator with PD compensation and sub-LSB duty control. IEEE J. Solid State Circuits 53(1), 35\u201349 (2018)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"5","key":"1_CR12","doi-asserted-by":"publisher","first-page":"130","DOI":"10.1109\/LSSC.2018.2875828","volume":"1","author":"SJ Kim","year":"2018","unstructured":"Kim, S.J., Kim, D., Ham, H., Kim, J., Seok, M.: A 67.1-ps FOM, 0.5-V-hybrid digital LDO with asynchronous feedforward control via slope detection and synchronous PI with state-based hysteresis clock switching. IEEE Solid State Circuits Lett. 1(5), 130\u2013133 (2018)","journal-title":"IEEE Solid State Circuits Lett."},{"issue":"9","key":"1_CR13","doi-asserted-by":"publisher","first-page":"8011","DOI":"10.1109\/TPEL.2017.2771942","volume":"33","author":"MA Akram","year":"2018","unstructured":"Akram, M.A., Hong, W., Hwang, I.: Fast transient fully standard-cell-based all digital low-dropout regulator with 99.97% current efficiency. IEEE Trans. Power Electron. 33(9), 8011\u20138019 (2018)","journal-title":"IEEE Trans. Power Electron."},{"issue":"6","key":"1_CR14","doi-asserted-by":"publisher","first-page":"154","DOI":"10.1109\/LSSC.2018.2885217","volume":"1","author":"L Zhao","year":"2018","unstructured":"Zhao, L., Lu, Y., Martins, R.P.: A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response. IEEE Solid State Circuits Lett. 1(6), 154\u2013157 (2018)","journal-title":"IEEE Solid State Circuits Lett."},{"key":"1_CR15","doi-asserted-by":"crossref","unstructured":"Liu, J., Maghari, N.: A fully-synthesizable 0.6\u00a0V digital LDO with dual-loop control using digital standard cells. In: Proceedings of IEEE International New Circuits and Systems Conference (NEWCAS), pp. 1\u20134, June 2016","DOI":"10.1109\/NEWCAS.2016.7604791"},{"issue":"1","key":"1_CR16","doi-asserted-by":"publisher","first-page":"84","DOI":"10.1109\/TCSI.2013.2268571","volume":"61","author":"S Weaver","year":"2014","unstructured":"Weaver, S., Hershberg, B., Moon, U.: Digitally synthesized stochastic flash ADC using only standard digital cells. IEEE Trans. Circuits Syst. I Reg. Pap. 61(1), 84\u201391 (2014)","journal-title":"IEEE Trans. Circuits Syst. I Reg. Pap."},{"issue":"1","key":"1_CR17","doi-asserted-by":"publisher","first-page":"68","DOI":"10.1109\/JSSC.2014.2348311","volume":"50","author":"W Deng","year":"2015","unstructured":"Deng, W., et al.: A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique. IEEE J. Solid State Circuits 50(1), 68\u201380 (2015)","journal-title":"IEEE J. Solid State Circuits"},{"key":"1_CR18","doi-asserted-by":"crossref","unstructured":"Ojima, N., Nakura, T., Iizuka, T., Asada, K.: A synthesizable digital low-dropout regulator based on voltage-to-time conversion. In: 26th IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), October 2018","DOI":"10.1109\/VLSI-SoC.2018.8644879"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-23425-6_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,25]],"date-time":"2023-06-25T00:03:26Z","timestamp":1687651406000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-23425-6_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030234249","9783030234256"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-23425-6_1","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"26 June 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Verona","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Italy","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"8 October 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"10 October 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"26","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vlsi-soc.di.univr.it\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}