{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T15:28:02Z","timestamp":1743002882396,"version":"3.40.3"},"publisher-location":"Cham","reference-count":29,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030234249"},{"type":"electronic","value":"9783030234256"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-23425-6_11","type":"book-chapter","created":{"date-parts":[[2019,6,25]],"date-time":"2019-06-25T14:06:41Z","timestamp":1561471601000},"page":"207-231","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection"],"prefix":"10.1007","author":[{"given":"Victor","family":"Champac","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andres","family":"Gomez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Freddy","family":"Forero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,6,26]]},"reference":[{"key":"11_CR1","doi-asserted-by":"crossref","unstructured":"Bhattacharya, A., Pal, S., Islam, A.: Implementation of FinFET based STT-MRAM bitcell. In: 2014 IEEE International Conference on Advanced Communications. Control and Computing Technologies, pp. 435\u2013439 (2014)","DOI":"10.1109\/ICACCCT.2014.7019480"},{"key":"11_CR2","unstructured":"ITRS International Technology Roadmap for Semiconductor. http:\/\/www.itrs2.net\/"},{"key":"11_CR3","doi-asserted-by":"crossref","unstructured":"Liu, Y., Xu, Q.: On modeling faults in FinFET logic circuits. In: 2012 IEEE International Test Conference, pp. 1\u20139 (2012)","DOI":"10.1109\/TEST.2012.6401565"},{"key":"11_CR4","doi-asserted-by":"crossref","unstructured":"Harutyunyan, G., Tshagharyan, G., Vardanian, V., Zorian, Y.: Fault modeling and test algorithm creation strategy for FinFET-based memories. In: 2014 IEEE 32nd VLSI Test Symposium (VTS), pp. 1\u20136 (2014)","DOI":"10.1109\/VTS.2014.6818747"},{"key":"11_CR5","doi-asserted-by":"crossref","unstructured":"Mesalles, F., Villacorta, H., Renovell, M., Champac, V.: Behavior and test of open-gate defects in FinFET based cells. In: 2016 21th IEEE European Test Symposium (ETS), pp. 1\u20136 (2016)","DOI":"10.1109\/ETS.2016.7519305"},{"key":"11_CR6","doi-asserted-by":"crossref","unstructured":"Panagopoulos, G., Augustine, C., Roy, K.: Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation. In: Proceedings of DRC, pp. 125\u2013126 (2011)","DOI":"10.1109\/DRC.2011.5994447"},{"key":"11_CR7","doi-asserted-by":"publisher","first-page":"1421","DOI":"10.1109\/TVLSI.2016.2630315","volume":"25","author":"R Bishnoi","year":"2017","unstructured":"Bishnoi, R., Oboril, F., Tahoori, M.B.: Design of defect and fault-tolerant nonvolatile spintronic flip-flops. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25, 1421\u20131432 (2017)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"11_CR8","doi-asserted-by":"crossref","unstructured":"Chintaluri, A., Parihar, A., Natarajan, S., Naeimi, H., Raychowdhury, A.: A model study of defects and faults in embedded spin transfer torque (STT) MRAM arrays. In: 2015 IEEE 24th Asian Test Symposium (ATS), pp. 187\u2013192 (2015)","DOI":"10.1109\/ATS.2015.39"},{"issue":"3","key":"11_CR9","doi-asserted-by":"publisher","first-page":"319","DOI":"10.1109\/JETCAS.2016.2547779","volume":"6","author":"A Chintaluri","year":"2016","unstructured":"Chintaluri, A., Naeimi, H., Natarajan, S., Raychowdhury, A.: Analysis of defects and variations in embedded spin transfer torque (STT) MRAM arrays. IEEE J. Emerg. Sel. Top. Circuits Syst. 6(3), 319\u2013329 (2016)","journal-title":"IEEE J. Emerg. Sel. Top. Circuits Syst."},{"issue":"16","key":"11_CR10","doi-asserted-by":"publisher","first-page":"165209","DOI":"10.1088\/0953-8984\/19\/16\/165209","volume":"19","author":"Z Diao","year":"2007","unstructured":"Diao, Z., et al.: Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory. J. Phys. Condens. Matter 19(16), 165209 (2007)","journal-title":"J. Phys. Condens. Matter"},{"key":"11_CR11","doi-asserted-by":"publisher","unstructured":"Vatajelu, E.I., Prinetto, P., Taouil, M., Hamdioui, S.: Challenges and solutions in emerging memory testing. IEEE Trans. Emerg. Top. Comput. (2017). https:\/\/doi.org\/10.1109\/TETC.2017.2691263","DOI":"10.1109\/TETC.2017.2691263"},{"key":"11_CR12","doi-asserted-by":"crossref","unstructured":"Wu, L., Taouil, M., Rao, S., Marinissen, E.J., Hamdioui, S.: Electrical modeling of STT-MRAM defects. In: 2018 IEEE International Test Conference (ITC), pp. 1\u201310 (2018)","DOI":"10.1109\/TEST.2018.8624749"},{"key":"11_CR13","doi-asserted-by":"crossref","unstructured":"Bishnoi, R., Ebrahimi, M., Oboril, F., Tahoori, M.B.: Read disturb fault detection in STT-MRAM. In: 2014 International Test Conference, Seattle, pp. 1\u20137 (2014)","DOI":"10.1109\/TEST.2014.7035342"},{"key":"11_CR14","doi-asserted-by":"crossref","unstructured":"Gomez, A.F., Forero, F., Roy, K., Champac, V.: Robust detection of bridge defects in STT-MRAM cells under process variations. In: 2018 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 65\u201370 (2018)","DOI":"10.1109\/VLSI-SoC.2018.8645022"},{"key":"11_CR15","doi-asserted-by":"publisher","first-page":"150","DOI":"10.1016\/j.microrel.2016.10.012","volume":"67","author":"AF Gomez","year":"2016","unstructured":"Gomez, A.F., et al.: Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations. Microelectron. Reliab. 67, 150\u2013158 (2016)","journal-title":"Microelectron. Reliab."},{"key":"11_CR16","unstructured":"Hosomi, M., et al.: A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM. In: IEEE International Electron Devices Meeting. IEDM Technical Digest, pp. 459\u2013462 (2005)"},{"key":"11_CR17","doi-asserted-by":"crossref","unstructured":"Andre, T., et al.: ST-MRAM fundamentals, challenges, and applications, In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, pp. 1\u20138 (2013)","DOI":"10.1109\/CICC.2013.6658449"},{"key":"11_CR18","doi-asserted-by":"publisher","first-page":"1449","DOI":"10.1109\/JPROC.2016.2521712","volume":"104","author":"X Fong","year":"2016","unstructured":"Fong, X., Kim, Y., Venkatesan, R., Choday, S.H., Raghunathan, A., Roy, K.: Spin-transfer torque memories: devices, circuits, and systems. Proc. IEEE 104, 1449\u20131488 (2016)","journal-title":"Proc. IEEE"},{"key":"11_CR19","doi-asserted-by":"publisher","first-page":"2472","DOI":"10.1103\/PhysRevLett.61.2472","volume":"61","author":"MN Baibich","year":"1988","unstructured":"Baibich, M.N., et al.: Giant magnetoresistance of (001) Fe\/(001) Cr magnetic superlattices. Phys. Rev. Lett. 61, 2472 (1988)","journal-title":"Phys. Rev. Lett."},{"issue":"12","key":"11_CR20","doi-asserted-by":"publisher","first-page":"868","DOI":"10.1038\/nmat1257","volume":"3","author":"S Yuasa","year":"2004","unstructured":"Yuasa, S., Nagahama, T., Fukushima, A., Suzuki, Y., Ando, K.: Giant room-temperature magnetoresistance in single-crystal Fe\/MgO\/Fe magnetic tunnel junctions. Nat. Mater. 3(12), 868 (2004)","journal-title":"Nat. Mater."},{"issue":"1","key":"11_CR21","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1109\/TNANO.2011.2169456","volume":"11","author":"X Fong","year":"2012","unstructured":"Fong, X., Choday, S.H., Roy, K.: Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching. IEEE Trans. Nanotechnol. 11(1), 172\u2013181 (2012)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"11_CR22","unstructured":"Hosomi, M., et al.: A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM. In: IEEE International Electron Devices Meeting, pp. 459\u2013462 (2005)"},{"key":"11_CR23","unstructured":"Fong, X., Choday, S.H., Georgios, P., Augustine, C., Roy, K.: Spice models for magnetic tunnel junctions based on monodomain approximation (2013)"},{"key":"11_CR24","unstructured":"Zhang, Y., Wang, X., Li, Y., Jones, A.K., Chen, Y.: Asymmetry of MTJ switching and its implication to STT-RAM designs. In: 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1313\u20131318 (2012)"},{"key":"11_CR25","doi-asserted-by":"publisher","first-page":"2962","DOI":"10.1109\/TMAG.2011.2158810","volume":"41","author":"Y Zhang","year":"2011","unstructured":"Zhang, Y., Wang, X., Li, H., Chen, Y.: STT-RAM cell optimization considering MTJ and CMOS variations. IEEE Trans. Magn. 41, 2962\u20132965 (2011)","journal-title":"IEEE Trans. Magn."},{"key":"11_CR26","doi-asserted-by":"crossref","unstructured":"Emre, Y., Yang, C., Sutaria, K., Cao, Y., Chakrabarti, C.: Enhancing the reliability of STT-RAM through circuit and system level techniques. In: 2012 IEEE Workshop on Signal Processing Systems, pp. 125\u2013130 (2012)","DOI":"10.1109\/SiPS.2012.11"},{"key":"11_CR27","doi-asserted-by":"crossref","unstructured":"Motaman, S., Ghosh, S., Rathi, N.: Impact of process-variations in STTRAM and adaptive boosting for robustness. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, pp. 1431\u20131436 (2015)","DOI":"10.7873\/DATE.2015.1018"},{"key":"11_CR28","unstructured":"Predictive technology models. http:\/\/ptm.asu.edu\/"},{"issue":"2","key":"11_CR29","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1007\/s10836-018-5714-0","volume":"34","author":"F Forero","year":"2018","unstructured":"Forero, F., Galliere, J.-M., Renovell, M., Champac, V.: Detectability challenges of bridge defects in finfet based logic cells. J. Electron. Test. 34(2), 123\u2013134 (2018)","journal-title":"J. Electron. Test."}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-23425-6_11","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,25]],"date-time":"2023-06-25T00:04:56Z","timestamp":1687651496000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-23425-6_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030234249","9783030234256"],"references-count":29,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-23425-6_11","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"26 June 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Verona","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Italy","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2018","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"8 October 2018","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"10 October 2018","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"26","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2018","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/vlsi-soc.di.univr.it\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}