{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,5]],"date-time":"2025-07-05T04:25:39Z","timestamp":1751689539564},"publisher-location":"Cham","reference-count":22,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030275617"},{"type":"electronic","value":"9783030275624"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-27562-4_3","type":"book-chapter","created":{"date-parts":[[2019,8,8]],"date-time":"2019-08-08T19:02:47Z","timestamp":1565290967000},"page":"34-47","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM"],"prefix":"10.1007","author":[{"given":"Deepak M.","family":"Mathew","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andr\u00e9 Lucas","family":"Chinazzo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Weis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthias","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bastien","family":"Giraud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pascal","family":"Vivet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexandre","family":"Levisse","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Norbert","family":"Wehn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,8,8]]},"reference":[{"key":"3_CR1","doi-asserted-by":"crossref","unstructured":"Chen, Y., Petti, C.: ReRAM technology evolution for storage class memory application. In: 46th European Solid-State Device Research Conference (ESSDERC), pp. 432\u2013435 (2016)","DOI":"10.1109\/ESSDERC.2016.7599678"},{"issue":"11","key":"3_CR2","doi-asserted-by":"publisher","first-page":"4374","DOI":"10.1109\/TED.2017.2746342","volume":"64","author":"SW Fong","year":"2017","unstructured":"Fong, S.W., Neumann, C.M., Wong, H.S.P.: Phase-change memory towards a storage-class memory. IEEE Trans. Electron Devices 64(11), 4374\u20134385 (2017)","journal-title":"IEEE Trans. Electron Devices"},{"key":"3_CR3","doi-asserted-by":"crossref","unstructured":"Cappelletti, P.: Non volatile memory evolution and revolution. In: 2015 IEEE International Electron Devices Meeting (IEDM), pp. 10.1.1\u201310.1.4 (2015)","DOI":"10.1109\/IEDM.2015.7409666"},{"issue":"4\/5","key":"3_CR4","doi-asserted-by":"publisher","first-page":"439","DOI":"10.1147\/rd.524.0439","volume":"52","author":"RF Freitas","year":"2008","unstructured":"Freitas, R.F., Wilcke, W.W.: Storage-class memory: the next storage system technology. IBM J. Res. Dev. 52(4\/5), 439\u2013447 (2008)","journal-title":"IBM J. Res. Dev."},{"key":"3_CR5","doi-asserted-by":"crossref","unstructured":"Lam, C.H.: Storage class memory. In: 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1080\u20131083 (2010)","DOI":"10.1109\/ICSICT.2010.5667551"},{"key":"3_CR6","doi-asserted-by":"crossref","unstructured":"Chen, A., Lin, M.: Variability of resistive switching memories and its impact on crossbar array performance. In: 2011 International Reliability Physics Symposium, pp. MY.7.1\u2013MY.7.4 (2011)","DOI":"10.1109\/IRPS.2011.5784590"},{"key":"3_CR7","doi-asserted-by":"crossref","unstructured":"Fantini, A., et al.: Intrinsic switching variability in HfO2RRAM. In: 5th IEEE International Memory Workshop, pp. 30\u201333 (2013)","DOI":"10.1109\/IMW.2013.6582090"},{"issue":"1","key":"3_CR8","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1186\/s11671-018-2619-x","volume":"13","author":"Y-F Kao","year":"2018","unstructured":"Kao, Y.-F., et al.: A study of the variability in contact resistive random access memory by stochastic vacancy model. Nanoscale Res. Lett. 13(1), 213 (2018)","journal-title":"Nanoscale Res. Lett."},{"key":"3_CR9","doi-asserted-by":"crossref","unstructured":"Xu, C., et al.: Overcoming the challenges of crossbar resistive memory architectures. In: IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp. 476\u2013488 (2015)","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"Ghofrani, A., Lastras-Montao, M.A., Cheng, K.: Toward large-scale access-transistor-free memristive crossbars. In: The 20th Asia and South Pacific Design Automation Conference, pp. 563\u2013568 (2015)","DOI":"10.1109\/ASPDAC.2015.7059067"},{"key":"3_CR11","unstructured":"JEDEC: DDR5 & NVDIMM-P Standards Under Development. \n                      https:\/\/www.jedec.org\/news\/pressreleases\/jedec-ddr5-nvdimm-p-standards-under-development"},{"key":"3_CR12","doi-asserted-by":"crossref","unstructured":"Poremba, M., et al.: DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1543\u20131546 (2015)","DOI":"10.7873\/DATE.2015.0733"},{"issue":"7","key":"3_CR13","doi-asserted-by":"publisher","first-page":"994","DOI":"10.1109\/TCAD.2012.2185930","volume":"31","author":"X Dong","year":"2012","unstructured":"Dong, X., et al.: NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 31(7), 994\u20131007 (2012)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst."},{"key":"3_CR14","doi-asserted-by":"crossref","unstructured":"Levisse, A., et al.: Architecture, design and technology guidelines for crosspoint memories. In: IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 55\u201360 (2017)","DOI":"10.1109\/NANOARCH.2017.8053733"},{"issue":"6","key":"3_CR15","doi-asserted-by":"publisher","first-page":"1951","DOI":"10.1109\/JPROC.2012.2190369","volume":"100","author":"HSP Wong","year":"2012","unstructured":"Wong, H.S.P., et al.: MetalOxide RRAM. Proc. IEEE 100(6), 1951\u20131970 (2012)","journal-title":"Proc. IEEE"},{"key":"3_CR16","doi-asserted-by":"publisher","first-page":"064015","DOI":"10.1103\/PhysRevApplied.6.064015","volume":"6","author":"K Fleck","year":"2016","unstructured":"Fleck, K., et al.: Uniting gradual and abrupt set processes in resistive switching oxides. Phys. Rev. Appl. 6, 064015 (2016)","journal-title":"Phys. Rev. Appl."},{"key":"3_CR17","unstructured":"Levisse, A., et al.: Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. In: IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 7\u201312 (2016)"},{"key":"3_CR18","doi-asserted-by":"crossref","unstructured":"Levisse, A., et al.: SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. In: 15th Non-Volatile Memory Technology Symposium (NVMTS), pp. 1\u20134 (2015)","DOI":"10.1109\/NVMTS.2015.7457426"},{"key":"3_CR19","doi-asserted-by":"crossref","unstructured":"Baek, J., et al.: A reliable cross-point MLC ReRAM with sneak current compensation. In: 2015 IEEE International Memory Workshop (IMW), pp. 1\u20134 (2015)","DOI":"10.1109\/IMW.2015.7150272"},{"key":"3_CR20","unstructured":"Liu, T., et al.: A 130.7 mm\n                      \n                        \n                      \n                      $$^2$$\n                     2-layer 32 Gb ReRAM memory device in 24 nm technology. In: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 210\u2013211 (2013)"},{"key":"3_CR21","doi-asserted-by":"crossref","unstructured":"Kim, S., Lee, W., Hwang, H.: Selector devices for cross-point ReRAM. In: 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, pp. 1\u20132 (2012)","DOI":"10.1109\/CNNA.2012.6331466"},{"key":"3_CR22","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544426","volume-title":"DRAM Circuit Design: Fundamental and High-Speed Topics, 2nd","author":"B Keeth","year":"2007","unstructured":"Keeth, B., et al.: DRAM Circuit Design: Fundamental and High-Speed Topics, 2nd. Wiley-IEEE Press, Hoboken (2007)"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-27562-4_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,8]],"date-time":"2019-08-08T19:12:20Z","timestamp":1565291540000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-27562-4_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030275617","9783030275624"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-27562-4_3","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"8 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SAMOS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Embedded Computer Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Pythagorion","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Greece","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"7 July 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 July 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"19","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"samos2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/www.samos-conference.com","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Softconf","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"55","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"26","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"47% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"2.5","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}