{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T10:43:13Z","timestamp":1743417793641},"publisher-location":"Cham","reference-count":19,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030275617"},{"type":"electronic","value":"9783030275624"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-27562-4_31","type":"book-chapter","created":{"date-parts":[[2019,8,8]],"date-time":"2019-08-08T19:02:47Z","timestamp":1565290967000},"page":"429-441","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing"],"prefix":"10.1007","author":[{"given":"Chirag","family":"Sudarshan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan","family":"Lappas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christian","family":"Weis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deepak M.","family":"Mathew","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthias","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Norbert","family":"Wehn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,8,8]]},"reference":[{"key":"31_CR1","doi-asserted-by":"crossref","unstructured":"Malossi, A.C.I., et al.: The transprecision computing paradigm: concept, design, and applications. In: 2018 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1105\u20131110, March 2018","DOI":"10.23919\/DATE.2018.8342176"},{"issue":"5","key":"31_CR2","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1109\/MM.2017.3711645","volume":"37","author":"D Rossi","year":"2017","unstructured":"Rossi, D., et al.: Energy-efficient near-threshold parallel computing: the PULPv2 cluster. IEEE Micro 37(5), 20\u201331 (2017)","journal-title":"IEEE Micro"},{"issue":"6","key":"31_CR3","doi-asserted-by":"publisher","first-page":"1566","DOI":"10.1007\/s10766-016-0473-y","volume":"45","author":"C Weis","year":"2017","unstructured":"Weis, C., et al.: DRAMSpec: a high-level DRAM timing, power and area exploration tool. Int. J. Parallel Program. 45(6), 1566\u20131591 (2017)","journal-title":"Int. J. Parallel Program."},{"key":"31_CR4","doi-asserted-by":"crossref","unstructured":"Jung, M., et al.: ConGen: an application specific dram memory controller generator. In: Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, pp. 257\u2013267. ACM, New York (2016)","DOI":"10.1145\/2989081.2989131"},{"key":"31_CR5","doi-asserted-by":"crossref","unstructured":"Bhati, I., et al.: Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. In: Proceedings of the 42nd Annual International Symposium on Computer Architecture, pp. 235\u2013246. ACM (2015)","DOI":"10.1145\/2872887.2750408"},{"key":"31_CR6","doi-asserted-by":"crossref","unstructured":"Liu, J., et al.: RAIDR: retention-aware intelligent dram refresh. In: Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA 2012, pp. 1\u201312. IEEE Computer Society, Washington (2012)","DOI":"10.1109\/ISCA.2012.6237001"},{"key":"31_CR7","doi-asserted-by":"crossref","unstructured":"Jung, M., et al.: Approximate computing with partially unreliable dynamic random access memory - approximate DRAM. In: Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, pp. 100:1\u2013100:4. ACM, New York (2016)","DOI":"10.1145\/2897937.2905002"},{"key":"31_CR8","unstructured":"Lucas, J., et al.: Sparkk: quality-scalable approximate storage in DRAM. In: The Memory Forum, June 2014"},{"issue":"3","key":"31_CR9","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1145\/1961296.1950391","volume":"46","author":"S Liu","year":"2011","unstructured":"Liu, S., et al.: Flikker: saving DRAM refresh-power through critical data partitioning. SIGPLAN Not. 46(3), 213\u2013224 (2011)","journal-title":"SIGPLAN Not."},{"key":"31_CR10","doi-asserted-by":"crossref","unstructured":"Jung, M.., et al.: Omitting refresh - a case study for commodity and wide I\/O DRAMs. In: 1st International Symposium on Memory Systems, MEMSYS 2015, Washington, DC, USA, October 2015","DOI":"10.1145\/2818950.2818964"},{"key":"31_CR11","doi-asserted-by":"crossref","unstructured":"Mathew, D.M., et al.: Using run-time reverse-engineering to optimize DRAM refresh. In: International Symposium on Memory Systems (MEMSYS17) (2017)","DOI":"10.1145\/3132402.3132419"},{"key":"31_CR12","unstructured":"Jedec Solid State Technology Association. DDR3 SDRAM (JESD 79\u20133) (2012)"},{"key":"31_CR13","unstructured":"Cadence Inc.: Cadence\u00ae Denali\u00ae DDR Memory IP, October 2014. \n                      http:\/\/ip.cadence.com\/ipportfolio\/ip-portfolio-overview\/memory-ip\/ddr-lpddr\n                      \n                    . Accessed 18 Feb 2015"},{"key":"31_CR14","unstructured":"Synopsys, Inc.: DesignWare DDR IP (2015). \n                      http:\/\/www.synopsys.com\/IP\/ InterfaceIP\/DDRn\/Pages\/\n                      \n                    . Accessed 18 Feb 2015"},{"key":"31_CR15","unstructured":"Fan, X., et al.: ESD protection circuit schemes for DDR3 DQ drivers. In: Electrical Overstress\/Electrostatic Discharge Symposium Proceedings, pp. 1\u20136 (2010)"},{"key":"31_CR16","unstructured":"Yoo, C., et al.: A 1.8 V 700 Mb\/s\/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration. In: 2003 IEEE International Solid-State Circuits Conference, ISSCC 2003. Digest of Technical Papers, vol. 1, pp. 312\u2013496, February 2003"},{"key":"31_CR17","doi-asserted-by":"crossref","unstructured":"Chen, S., et al.: An all-digital delay-locked loop for high-speed memory interface applications. In: Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, pp. 1\u20134, April 2014","DOI":"10.1109\/VLSI-DAT.2014.6834900"},{"issue":"1","key":"31_CR18","doi-asserted-by":"publisher","first-page":"55","DOI":"10.1109\/TVLSI.2011.2181547","volume":"21","author":"D Caro De","year":"2013","unstructured":"De Caro, D.: Glitch-free NAND-based digitally controlled delay-lines. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(1), 55\u201366 (2013)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"31_CR19","unstructured":"Micron: DDR3 SDRAM System Power Calculator, July 2011. Accessed 03 July 2014"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-27562-4_31","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,8]],"date-time":"2019-08-08T19:15:18Z","timestamp":1565291718000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-27562-4_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030275617","9783030275624"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-27562-4_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"8 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SAMOS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Embedded Computer Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Pythagorion","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Greece","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"7 July 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 July 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"19","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"samos2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/www.samos-conference.com","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Softconf","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"55","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"26","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"47% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"2.5","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}