{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T17:57:02Z","timestamp":1772906222382,"version":"3.50.1"},"publisher-location":"Cham","reference-count":17,"publisher":"Springer International Publishing","isbn-type":[{"value":"9783030296100","type":"print"},{"value":"9783030296117","type":"electronic"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-29611-7_1","type":"book-chapter","created":{"date-parts":[[2019,8,12]],"date-time":"2019-08-12T23:02:59Z","timestamp":1565650979000},"page":"3-14","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":16,"title":["RV-CNN: Flexible and Efficient Instruction Set for CNNs Based on RISC-V Processors"],"prefix":"10.1007","author":[{"given":"Wenqi","family":"Lou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chao","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Gong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuehai","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2019,8,9]]},"reference":[{"key":"1_CR1","doi-asserted-by":"crossref","unstructured":"Banakar, R., Steinke, S., Lee, B.S., Balakrishnan, M., Marwedel, P.: Scratchpad memory: a design alternative for cache on-chip memory in embedded systems. In: International Symposium on Hardware\/software Codesign (2002)","DOI":"10.1145\/774801.774805"},{"key":"1_CR2","doi-asserted-by":"crossref","unstructured":"Chen, T., et al.: DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning. In: ACM SIGPLAN Notices, vol. 49, pp. 269\u2013284. ACM (2014)","DOI":"10.1145\/2644865.2541967"},{"key":"1_CR3","doi-asserted-by":"crossref","unstructured":"Chen, Y., Luo, T., Liu, S., Zhang, S., He, L., et al.: DaDianNao: a machine-learning supercomputer. In: Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture, pp. 609\u2013622. IEEE Computer Society (2014)","DOI":"10.1109\/MICRO.2014.58"},{"key":"1_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"281","DOI":"10.1007\/978-3-319-11179-7_36","volume-title":"Artificial Neural Networks and Machine Learning \u2013 ICANN 2014","author":"J Cong","year":"2014","unstructured":"Cong, J., Xiao, B.: Minimizing computation in convolutional neural networks. In: Wermter, S., et al. (eds.) ICANN 2014. LNCS, vol. 8681, pp. 281\u2013290. Springer, Cham (2014). https:\/\/doi.org\/10.1007\/978-3-319-11179-7_36"},{"issue":"3","key":"1_CR5","doi-asserted-by":"publisher","first-page":"339","DOI":"10.1007\/s11265-015-1070-9","volume":"84","author":"F Conti","year":"2016","unstructured":"Conti, F., Rossi, D., Pullini, A., Loi, I., Benini, L.: PULP: a ultra-low power parallel accelerator for energy-efficient and flexible embedded vision. J. Signal Process. Syst. 84(3), 339\u2013354 (2016)","journal-title":"J. Signal Process. Syst."},{"key":"1_CR6","doi-asserted-by":"crossref","unstructured":"Flamand, E., et al.: GAP-8: a RISC-V SoC for AI at the edge of the IoT. In: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 1\u20134. IEEE (2018)","DOI":"10.1109\/ASAP.2018.8445101"},{"key":"1_CR7","doi-asserted-by":"crossref","unstructured":"Gokhale, V., Jin, J., Dundar, A., Martini, B., Culurciello, E.: A 240 G-ops\/s mobile coprocessor for deep neural networks. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, pp. 682\u2013687 (2014)","DOI":"10.1109\/CVPRW.2014.106"},{"issue":"11","key":"1_CR8","doi-asserted-by":"publisher","first-page":"2601","DOI":"10.1109\/TCAD.2018.2857078","volume":"37","author":"L Gong","year":"2018","unstructured":"Gong, L., Wang, C., Li, X., Chen, H., Zhou, X.: MALOC: a fully pipelined fpga accelerator for convolutional neural networks with all layers mapped on chip. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 37(11), 2601\u20132612 (2018)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"1_CR9","unstructured":"Krizhevsky, A., Sutskever, I., Hinton, G.E.: ImageNet classification with deep convolutional neural networks. In: Advances in Neural Information Processing Systems, pp. 1097\u20131105 (2012)"},{"issue":"11","key":"1_CR10","doi-asserted-by":"publisher","first-page":"2278","DOI":"10.1109\/5.726791","volume":"86","author":"Y LeCun","year":"1998","unstructured":"LeCun, Y., Bottou, L., Bengio, Y., Haffner, P., et al.: Gradient-based learning applied to document recognition. Proc. IEEE 86(11), 2278\u20132324 (1998)","journal-title":"Proc. IEEE"},{"key":"1_CR11","doi-asserted-by":"crossref","unstructured":"Liu, S., et al.: Cambricon: an instruction set architecture for neural networks. In: ACM SIGARCH Computer Architecture News, vol. 44, pp. 393\u2013405. IEEE Press (2016)","DOI":"10.1145\/3007787.3001179"},{"issue":"10","key":"1_CR12","doi-asserted-by":"publisher","first-page":"1217","DOI":"10.1109\/TCSII.2017.2690919","volume":"64","author":"S Moini","year":"2017","unstructured":"Moini, S., Alizadeh, B., Ebrahimpour, R.: A resource-limited hardware accelerator for convolutional neural networks in embedded vision applications. IEEE Trans. Circuits Syst. II: Express Briefs 64(10), 1217\u20131221 (2017)","journal-title":"IEEE Trans. Circuits Syst. II: Express Briefs"},{"key":"1_CR13","unstructured":"Simonyan, K., Zisserman, A.: Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556 (2014)"},{"key":"1_CR14","unstructured":"Sun, Y., Chen, Y., Wang, X., Tang, X.: Deep learning face representation by joint identification-verification. In: Advances in Neural Information Processing Systems, pp. 1988\u20131996 (2014)"},{"issue":"3","key":"1_CR15","first-page":"513","volume":"36","author":"C Wang","year":"2016","unstructured":"Wang, C., Gong, L., Yu, Q., Li, X., Xie, Y., Zhou, X.: DLAU: a scalable deep learning accelerator unit on FPGA. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 36(3), 513\u2013517 (2016)","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"issue":"10","key":"1_CR16","doi-asserted-by":"publisher","first-page":"2993","DOI":"10.1109\/TPDS.2017.2701828","volume":"28","author":"C Wang","year":"2017","unstructured":"Wang, C., Li, X., Chen, Y., Zhang, Y., Diessel, O., Zhou, X.: Service-oriented architecture on FPGA-based MPSoC. IEEE Trans. Parallel Distrib. Syst. 28(10), 2993\u20133006 (2017)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"1_CR17","doi-asserted-by":"crossref","unstructured":"Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., Cong, J.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161\u2013170. ACM (2015)","DOI":"10.1145\/2684746.2689060"}],"container-title":["Lecture Notes in Computer Science","Advanced Parallel Processing Technologies"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-29611-7_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,1,16]],"date-time":"2021-01-16T14:33:58Z","timestamp":1610807638000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-29611-7_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030296100","9783030296117"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-29611-7_1","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"9 August 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"APPT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Advanced Parallel Processing Technologies","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Tianjin","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"15 August 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16 August 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"13","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"appt2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/tc.ccf.org.cn\/tcarch\/appt2019\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}