{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T12:13:28Z","timestamp":1743077608341,"version":"3.40.3"},"publisher-location":"Cham","reference-count":13,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030307080"},{"type":"electronic","value":"9783030307097"}],"license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019]]},"DOI":"10.1007\/978-3-030-30709-7_33","type":"book-chapter","created":{"date-parts":[[2019,9,28]],"date-time":"2019-09-28T18:25:28Z","timestamp":1569695128000},"page":"355-360","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["SIRM: Shift Insensitive Racetrack Main Memory"],"prefix":"10.1007","author":[{"given":"Hongbin","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Bo","family":"Wei","sequence":"additional","affiliation":[]},{"given":"Youyou","family":"Lu","sequence":"additional","affiliation":[]},{"given":"Jiwu","family":"Shu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2019,9,29]]},"reference":[{"key":"33_CR1","unstructured":"Zhang, C., et al.: Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. In: Proceedings of the 20th Asia and South Pacific Design Automation Conference, Chiba, Japan, January 2015, pp. 100\u2013105 (2015)"},{"issue":"5","key":"33_CR2","first-page":"629","volume":"63","author":"Y Zhang","year":"2016","unstructured":"Zhang, Y., et al.: Perspectives of racetrack memory for large-capacity on-chip memory: from device to system. IEEE Trans. Circ. Syst. 63(5), 629\u2013638 (2016)","journal-title":"IEEE Trans. Circ. Syst."},{"key":"33_CR3","doi-asserted-by":"crossref","unstructured":"Sun, G., et al.: From device to system: cross-layer design exploration of racetrack memory. In: Proceedings of the 18th Design, Automation and Test in Europe (DATE), Grenoble, France, 9\u201313 March 2015, pp. 1018\u20131023 (2015)","DOI":"10.7873\/DATE.2015.1121"},{"issue":"5873","key":"33_CR4","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1126\/science.1145799","volume":"320","author":"SS Parkin","year":"2008","unstructured":"Parkin, S.S., Hayashi, M., Thomas, L.: Magnetic domain-wall racetrack memory. Science 320(5873), 190\u2013194 (2008)","journal-title":"Science"},{"key":"33_CR5","doi-asserted-by":"crossref","unstructured":"Venkatesan R, et al.: TapeCache: a high density, energy efficient cache based on domain wall memory. In: Proceedings of the 2012 ACM\/IEEE International Symposium on Low Power Electronics and Design, pp. 185\u2013190. ACM (2012)","DOI":"10.1145\/2333660.2333707"},{"key":"33_CR6","doi-asserted-by":"crossref","unstructured":"Mao, H., et al.: Exploring data placement in racetrack memory based scratchpad memory. In: Proceedings of the 4th IEEE Non-Volatile Memory System and Applications Symposium, Hong Kong, China, August 2015, pp. 1\u20135 (2015)","DOI":"10.1109\/NVMSA.2015.7304358"},{"key":"33_CR7","doi-asserted-by":"crossref","unstructured":"Chen, X., et al.: Optimizing data placement for reducing shift operations on Domain Wall Memories. In: Design Automation Conference, pp. 1\u20136. ACM (2015)","DOI":"10.1145\/2744769.2744883"},{"key":"33_CR8","doi-asserted-by":"crossref","unstructured":"Hu, Q., et al.: Exploring main memory design based on racetrack memory technology. In: Proceedings of the 26th ACM Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, USA, 18\u201320 May 2016, pp. 397\u2013402 (2016)","DOI":"10.1145\/2902961.2902967"},{"key":"33_CR9","unstructured":"Micron. 8Gb: x4, x8, x16 DDR4 SDRAM Description (2016). www.micron.com"},{"key":"33_CR10","doi-asserted-by":"crossref","unstructured":"Dong, X., et al.: NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 31(7), 994\u20131007 (2012)","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"33_CR11","unstructured":"https:\/\/en.wikipedia.org\/wiki\/DDR4_SDRA#Mcite_note-JESD79-3F-3"},{"key":"33_CR12","volume-title":"Memory Systems: Cache, DRAM, Disk","author":"B Jacob","year":"2010","unstructured":"Jacob, B., et al.: Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann, San Francisco (2010)"},{"key":"33_CR13","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert, N., Beckmann, B., Black, G., et al.: The gem5 simulator. SIGARCH Comput. Archit. 39, 1\u20137 (2011)","journal-title":"SIGARCH Comput. Archit."}],"container-title":["Lecture Notes in Computer Science","Network and Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-30709-7_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,28]],"date-time":"2023-09-28T00:06:06Z","timestamp":1695859566000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-30709-7_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019]]},"ISBN":["9783030307080","9783030307097"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-30709-7_33","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2019]]},"assertion":[{"value":"29 September 2019","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"NPC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP International Conference on Network and Parallel Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Hohhot","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"China","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23 August 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"24 August 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"npc2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/epcc.sjtu.edu.cn\/NPC2019","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}