{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T08:18:25Z","timestamp":1742977105171,"version":"3.40.3"},"publisher-location":"Cham","reference-count":29,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030445331"},{"type":"electronic","value":"9783030445348"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-44534-8_10","type":"book-chapter","created":{"date-parts":[[2020,3,25]],"date-time":"2020-03-25T06:03:05Z","timestamp":1585116185000},"page":"121-135","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":13,"title":["Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs"],"prefix":"10.1007","author":[{"given":"Pascal","family":"Bacchus","sequence":"first","affiliation":[]},{"given":"Robert","family":"Stewart","sequence":"additional","affiliation":[]},{"given":"Ekaterina","family":"Komendantskaya","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,3,25]]},"reference":[{"unstructured":"Abadi, M., et al.: TensorFlow: large-scale machine learning on heterogeneous systems (2015). \nhttps:\/\/www.tensorflow.org\/lite\n\n, software available from tensorflow.org","key":"10_CR1"},{"unstructured":"Al-Rfou, R., et al.: Theano: a Python framework for fast computation of mathematical expressions. CoRR abs\/1605.02688 (2016). \nhttp:\/\/arxiv.org\/abs\/1605.02688","key":"10_CR2"},{"issue":"3","key":"10_CR3","first-page":"16:1","volume":"11","author":"M Blott","year":"2018","unstructured":"Blott, M., et al.: FINN-R: an end-to-end deep-learning framework for fast exploration of quantized neural networks. Trans. Reconfigurable Technol. Syst. 11(3), 16:1\u201316:23 (2018)","journal-title":"Trans. Reconfigurable Technol. Syst."},{"doi-asserted-by":"crossref","unstructured":"Chen, T., et al.: DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning. In: ASPLOS 2014, Salt Lake City, UT, USA, 1\u20135 March 2014, pp. 269\u2013284. ACM (2014)","key":"10_CR4","DOI":"10.1145\/2654822.2541967"},{"unstructured":"Cheng, Y., Yu, F.X., Feris, R.S., Kumar, S., Choudhary, A.N., Chang, S.: Fast neural networks with circulant projections. CoRR abs\/1502.03436 (2015)","key":"10_CR5"},{"unstructured":"Courbariaux, M., Bengio, Y.: BinaryNet: training deep neural networks with weights and activations constrained to +1 or $$-$$1. CoRR abs\/1602.02830 (2016)","key":"10_CR6"},{"doi-asserted-by":"crossref","unstructured":"DiCecco, R., Lacey, G., Vasiljevic, J., Chow, P., Taylor, G.W., Areibi, S.: Caffeinated FPGAs: FPGA framework for convolutional neural networks. In: FPT 2016, Xi\u2019an, China, 7\u20139 December 2016, pp. 265\u2013268. IEEE (2016)","key":"10_CR7","DOI":"10.1109\/FPT.2016.7929549"},{"doi-asserted-by":"publisher","unstructured":"Dieleman, S., et al.: Lasagne: first release, August 2015. \nhttps:\/\/doi.org\/10.5281\/zenodo.27878","key":"10_CR8","DOI":"10.5281\/zenodo.27878"},{"doi-asserted-by":"crossref","unstructured":"Ding, C., Wang, S., Liu, N., Xu, K., Wang, Y., Liang, Y.: REQ-YOLO: a resource-aware, efficient quantization framework for object detection on FPGAs. In: FPGA 2019, Seaside, CA, USA, 24\u201326 February 2019, pp. 33\u201342. ACM (2019)","key":"10_CR9","DOI":"10.1145\/3289602.3293904"},{"unstructured":"Ghasemzadeh, M., Samragh, M., Koushanfar, F.: ResBinNet: residual binary neural network. CoRR abs\/1711.01243 (2017)","key":"10_CR10"},{"unstructured":"Han, S., Pool, J., Tran, J., Dally, W.J.: Learning both weights and connections for efficient neural network. In: Advances in Neural Information Processing Systems 28: Annual Conference on Neural Information Processing Systems 2015, Montreal, Quebec, Canada, 7\u201312 December 2015, pp. 1135\u20131143 (2015)","key":"10_CR11"},{"key":"10_CR12","first-page":"187:1","volume":"18","author":"I Hubara","year":"2017","unstructured":"Hubara, I., Courbariaux, M., Soudry, D., El-Yaniv, R., Bengio, Y.: Quantized neural networks: training neural networks with low precision weights and activations. J. Mach. Learn. Res. 18, 187:1\u2013187:30 (2017)","journal-title":"J. Mach. Learn. Res."},{"unstructured":"Intel: Intel OpenVino Toolkit. \nhttps:\/\/software.intel.com\/en-us\/openvino-toolkit","key":"10_CR13"},{"unstructured":"LeCun, Y., Cortes, C.: The MNIST database of handwritten digits (1998)","key":"10_CR14"},{"key":"10_CR15","doi-asserted-by":"publisher","first-page":"1072","DOI":"10.1016\/j.neucom.2017.09.046","volume":"275","author":"S Liang","year":"2018","unstructured":"Liang, S., Yin, S., Liu, L., Luk, W., Wei, S.: FP-BNN: binarized neural network on FPGA. Neurocomputing 275, 1072\u20131086 (2018)","journal-title":"Neurocomputing"},{"unstructured":"Lu, D.: Creating an AI can be five times worse for the planet than a car, June 2019. \nhttps:\/\/www.newscientist.com\/article\/2205779-creating-an-ai-can-be-five-times-worse-for-the-planet-than-a-car\/\n\n, new Scientist","key":"10_CR16"},{"doi-asserted-by":"crossref","unstructured":"Park, J., Sung, W.: FPGA based implementation of deep neural networks using on-chip memory only. In: ICASSP 2016, Shanghai, China, 20\u201325 March 2016, pp. 1011\u20131015. IEEE (2016)","key":"10_CR17","DOI":"10.1109\/ICASSP.2016.7471828"},{"doi-asserted-by":"crossref","unstructured":"Qiu, J., et al.: Going deeper with embedded FPGA platform for convolutional neural network. In: Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 21\u201323 February 2016, pp. 26\u201335. ACM (2016)","key":"10_CR18","DOI":"10.1145\/2847263.2847265"},{"doi-asserted-by":"crossref","unstructured":"Radu, V., et al.: Performance aware convolutional neural network channel pruning for embedded GPUs. In: IISWC 2019. IEEE, October 2019","key":"10_CR19","DOI":"10.1109\/IISWC47752.2019.9042000"},{"doi-asserted-by":"crossref","unstructured":"Rybalkin, V., Pappalardo, A., Ghaffar, M.M., Gambardella, G., Wehn, N., Blott, M.: FINN-L: library extensions and design trade-off analysis for variable precision LSTM networks on FPGAs. In: FPL 2018, Dublin, Ireland, 27\u201331 August 2018, pp. 89\u201396. IEEE Computer Society (2018)","key":"10_CR20","DOI":"10.1109\/FPL.2018.00024"},{"key":"10_CR21","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1007\/978-3-319-78890-6_3","volume-title":"Applied Reconfigurable Computing. Architectures, Tools, and Applications","author":"J Su","year":"2018","unstructured":"Su, J., et al.: Accuracy to throughput trade-offs for\u00a0reduced precision neural networks on\u00a0reconfigurable logic. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P.C. (eds.) ARC 2018. LNCS, vol. 10824, pp. 29\u201342. Springer, Cham (2018). \nhttps:\/\/doi.org\/10.1007\/978-3-319-78890-6_3"},{"doi-asserted-by":"crossref","unstructured":"Umuroglu, Y., et al.: FINN: a framework for fast, scalable binarized neural network inference. In: FPGA 2017, Monterey, CA, USA, 22\u201324 February 2017, pp. 65\u201374. ACM (2017)","key":"10_CR22","DOI":"10.1145\/3020078.3021744"},{"issue":"2","key":"10_CR23","doi-asserted-by":"publisher","first-page":"326","DOI":"10.1109\/TNNLS.2018.2844093","volume":"30","author":"SI Venieris","year":"2019","unstructured":"Venieris, S.I., Bouganis, C.: fpgaConvNet: mapping regular and irregular convolutional neural networks on FPGAs. IEEE Trans. Neural Netw. Learn. Syst. 30(2), 326\u2013342 (2019)","journal-title":"IEEE Trans. Neural Netw. Learn. Syst."},{"doi-asserted-by":"crossref","unstructured":"V\u00e9stias, M.P., Neto, H.C.: Trends of CPU, GPU and FPGA for high-performance computing. In: FPL 2014, Munich, Germany, 2\u20134 September 2014, pp. 1\u20136. IEEE (2014)","key":"10_CR24","DOI":"10.1109\/FPL.2014.6927483"},{"issue":"2","key":"10_CR25","first-page":"40:1","volume":"52","author":"E Wang","year":"2019","unstructured":"Wang, E., et al.: Deep neural network approximation for custom hardware: where we\u2019ve been, where we\u2019re going. ACM Comput. Surv. 52(2), 40:1\u201340:39 (2019)","journal-title":"ACM Comput. Surv."},{"doi-asserted-by":"crossref","unstructured":"Wang, J., Lou, Q., Zhang, X., Zhu, C., Lin, Y., Chen, D.: Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA. In: FPL 2018, Dublin, Ireland, 27\u201331 August, pp. 163\u2013169. IEEE Computer Society (2018)","key":"10_CR26","DOI":"10.1109\/FPL.2018.00035"},{"doi-asserted-by":"crossref","unstructured":"Zhang, Q., Cao, J., Zhang, Y., Zhang, S., Zhang, Q., Yu, D.: FPGA implementation of quantized convolutional neural networks. In: ICCT 2019, Xi\u2019an, China, 16\u201319 October, pp. 1605\u20131610. IEEE (2019)","key":"10_CR27","DOI":"10.1109\/ICCT46805.2019.8947168"},{"doi-asserted-by":"crossref","unstructured":"Zhao, Y., et al.: Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs. In: ICFPT 2019, Tianjin, China, 9\u201313 December 2019, pp. 45\u201353. IEEE (2019)","key":"10_CR28","DOI":"10.1109\/ICFPT47387.2019.00014"},{"doi-asserted-by":"publisher","unstructured":"Zmora, N., Jacob, G., Zlotnik, L., Elharar, B., Novik, G.: Neural network distiller (2018). \nhttps:\/\/doi.org\/10.5281\/zenodo.1297430","key":"10_CR29","DOI":"10.5281\/zenodo.1297430"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing. Architectures, Tools, and Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-44534-8_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,29]],"date-time":"2020-07-29T16:08:26Z","timestamp":1596038906000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-44534-8_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030445331","9783030445348"],"references-count":29,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-44534-8_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"25 March 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Applied Reconfigurable Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Toledo","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Spain","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2020","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1 April 2020","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"3 April 2020","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arc2020","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/arcoresearch.com\/arc2020\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"40","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"18","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"45% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"11 poster presentations","order":10,"name":"additional_info_on_review_process","label":"Additional Info on Review Process","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}