{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,20]],"date-time":"2025-09-20T19:19:22Z","timestamp":1758395962681,"version":"3.40.3"},"publisher-location":"Cham","reference-count":28,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030445331"},{"type":"electronic","value":"9783030445348"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-44534-8_16","type":"book-chapter","created":{"date-parts":[[2020,3,25]],"date-time":"2020-03-25T06:03:05Z","timestamp":1585116185000},"page":"211-220","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0891-235X","authenticated-orcid":false,"given":"Hector Gerardo Munoz","family":"Hernandez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7714-510X","authenticated-orcid":false,"given":"Safdar","family":"Mahmood","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0012-7023","authenticated-orcid":false,"given":"Marcelo","family":"Brandalero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1790-3869","authenticated-orcid":false,"given":"Michael","family":"H\u00fcbner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,3,25]]},"reference":[{"key":"16_CR1","unstructured":"Abdelouahab, K., Pelcat, M., Serot, J., Berry, F.: Accelerating CNN inference on FPGAs: a Survey (2018). \narXiv: 1806.01683\n\n [cs.DC]"},{"key":"16_CR2","doi-asserted-by":"crossref","unstructured":"Bacis, M., Natale, G., Del Sozzo, E., Santambrogio, M.D.: A pipelined and scalable dataflow implementation of convolutional neural networks on FPGA. In: 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2017, pp. 90\u201397 (2017)","DOI":"10.1109\/IPDPSW.2017.44"},{"key":"16_CR3","unstructured":"Bhandare, A., Bhide, M.V., Gokhale, P., Chandavarkar, R.: Applications of Convolutional Neural Networks (2016)"},{"key":"16_CR4","unstructured":"Courbariaux, M., Hubara, I., Soudry, D., El-Yaniv, R. Bengio, Y.: Binarized neural networks: training deep neural networks with weights and activations constrained to +1 or $$-$$1 (2016). \narXiv: 1602.02830\n\n [cs.LG]"},{"key":"16_CR5","doi-asserted-by":"crossref","unstructured":"Farabet, C., et al.: Hardware accelerated convolutional neural networks for synthetic vision systems. In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems, May 2010, pp. 257\u2013260 (2010)","DOI":"10.1109\/ISCAS.2010.5537908"},{"key":"16_CR6","unstructured":"Fu, C., Zhu, S., Su, H., Lee, C.-E., Zhao, J.: Towards fast and energy-efficient binarized neural network inference on FPGA (2018). \narXiv: 1810.02068\n\n [cs.LG]"},{"key":"16_CR7","doi-asserted-by":"publisher","first-page":"455","DOI":"10.1016\/0031-3203(82)90024-3","volume":"15","author":"K Fukushima","year":"1982","unstructured":"Fukushima, K., Miyake, S.: Neocognitron: a new algorithm for pattern recognition tolerant of deformations and shifts in position. Pattern Recogn. 15, 455\u2013469 (1982)","journal-title":"Pattern Recogn."},{"key":"16_CR8","unstructured":"Guan, Y., et al.: FP-DNN: an automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates. In: 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2017, pp. 152\u2013159, IEEE Computer Society, Los Alamitos (2017). \nhttps:\/\/doi.ieeecomputersociety.org\/10.1109\/FCCM.2017.25"},{"key":"16_CR9","doi-asserted-by":"crossref","unstructured":"Hailesellasie, M., Hasan, S.R., Mohamed, O.A.: MulMapper: towards an automated FPGA-Based CNN processor generator based on a dynamic design space exploration. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), May 2019, pp. 1\u20135 (2019)","DOI":"10.1109\/ISCAS.2019.8702589"},{"key":"16_CR10","unstructured":"Hao, Y.: A general neural network hardware architecture on FPGA (2017). \narXiv: 1711.05860\n\n [cs.CV]"},{"key":"16_CR11","doi-asserted-by":"crossref","unstructured":"Huang, C., Ni, S., Chen, G.: A layer-based structured design of CNN on FPGA. In: 2017 IEEE 12th International Conference on ASIC (ASICON), October 2017, pp. 1037\u20131040 (2017)","DOI":"10.1109\/ASICON.2017.8252656"},{"key":"16_CR12","unstructured":"Hubara, I., Courbariaux, M., Soudry, D., El-Yaniv, R., Bengio, Y.: Quantized neural networks: training neural networks with low precision weights and activations (2016). \narXiv: 1609.07061\n\n [cs.NE]"},{"key":"16_CR13","unstructured":"Iandola, F.N., et al.: SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and $$<$$0.5MB model size (2016). \narXiv: 1602.07360\n\n [cs.CV]"},{"key":"16_CR14","doi-asserted-by":"crossref","unstructured":"Jia, Y., et al.: Caffe: convolutional architecture for fast feature embedding. arXiv preprint\narXiv:1408.5093\n\n (2014)","DOI":"10.1145\/2647868.2654889"},{"key":"16_CR15","unstructured":"Kluyver, T., et al.: Jupyter notebooks - a publishing format for reproducible computational workflows. In: Loizides, F., Scmidt, B. (eds.) Positioning and Power in Academic Publishing: Players, Agents and Agendas, pp. 87\u201390. IOS Press, Amsterdam (2016). \nhttps:\/\/eprints.soton.ac.uk\/403913\/"},{"key":"16_CR16","unstructured":"LeCun, Y., et al.: In: Touretzky, D.S. (ed.) Advances in Neural Information Processing Systems 2, pp. 396\u2013404. Morgan-Kaufmann, Burlington (1990). \nhttp:\/\/papers.nips.cc\/paper\/293-handwritten-digit-recognition-with-a-back-propagation-network.pdf"},{"key":"16_CR17","doi-asserted-by":"crossref","unstructured":"Leon, V., et al.: A tensorflow extension framework for optimized generation of hardware CNN inference engines in technologies 2020, MDPI 2020. \nhttps:\/\/www.mdpi.com\/2227-7080\/8\/1\/6","DOI":"10.3390\/technologies8010006"},{"key":"16_CR18","doi-asserted-by":"crossref","unstructured":"Li, P., Li, J., Wang, G.: Application of convolutional neural network in natural language processing. In: 2018 15th International Computer Conference on Wavelet Active Media Technology and Information Processing (ICCWAMTIP), December 2018, pp. 120\u2013122 (2018)","DOI":"10.1109\/ICCWAMTIP.2018.8632576"},{"key":"16_CR19","doi-asserted-by":"crossref","unstructured":"Natale, G., Bacis, M., Santambrogio, M.D.: On how to design dataflow FPGA-based accelerators for convolutional neural networks. In: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2017, pp. 639\u2013644 (2017)","DOI":"10.1109\/ISVLSI.2017.126"},{"key":"16_CR20","unstructured":"Nielsen, M.: Neural Network and Deep Learning. Determination Press. \nhttp:\/\/neuralnetworksanddeeplearning.com\/"},{"key":"16_CR21","unstructured":"Noronha, D.H., Salehpour, B., Wilton, S.J.E.: LeFlow: enabling flexible FPGA high-level synthesis of tensorflow deep neural networks (2018). \narXiv: 1807.05317\n\n [cs.LG]"},{"key":"16_CR22","unstructured":"Ovtcharov, K., et al.: Accelerating deep convolutional neural networks using specialized hardware, February 2015. \nhttps:\/\/www.microsoft.com\/en-us\/research\/publication\/accelerating-deep-convolutional-neural-networks-using-specialized-hardware\/"},{"key":"16_CR23","unstructured":"Solovyev, R.A., Kalinin, A.A., Kustov, A.G., Telpukhov, D.V., Ruhlov, V.S.: FPGA Implementation of Convolutional Neural Networks with Fixed-Point Calculations (2018). \narXiv: 1808.09945\n\n [cs.CV]"},{"key":"16_CR24","doi-asserted-by":"crossref","unstructured":"Umuroglu, Y., et al.: FINN. In: Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA 2017 (2017). \nhttp:\/\/dx.doi.org\/10.1145\/3020078.3021744","DOI":"10.1145\/3020078.3021744"},{"key":"16_CR25","unstructured":"Venieris, S.I., Kouris, A., Bouganis, C.-S.: Toolflows for mapping convolutional neural networks on FPGAs: a survey and future directions (2018). \narXiv: 1803.05900\n\n [cs.CV]"},{"key":"16_CR26","doi-asserted-by":"crossref","unstructured":"Wang, E., Davis, J.J., Cheung, P.Y.K.: A PYNQ-based framework for rapid CNN prototyping. In: 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2018, p. 223 (2018)","DOI":"10.1109\/FCCM.2018.00057"},{"key":"16_CR27","unstructured":"Ma, Y., Suda, N., Cao, Y., Seo, J., Vrudhula, S.: Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. In: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), August 2016, pp. 1\u20138 (2016)"},{"key":"16_CR28","doi-asserted-by":"crossref","unstructured":"Zaheer, R., Shaziya, H.: GPU-based empirical evaluation of activation functions in convolutional neural networks. In: 2018 2nd International Conference on Inventive Systems and Control (ICISC), January 2018, pp. 769\u2013773 (2018)","DOI":"10.1109\/ICISC.2018.8398903"}],"container-title":["Lecture Notes in Computer Science","Applied Reconfigurable Computing. Architectures, Tools, and Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-44534-8_16","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,29]],"date-time":"2020-07-29T16:08:56Z","timestamp":1596038936000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-44534-8_16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030445331","9783030445348"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-44534-8_16","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"25 March 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Symposium on Applied Reconfigurable Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Toledo","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Spain","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2020","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1 April 2020","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"3 April 2020","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arc2020","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/arcoresearch.com\/arc2020\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"40","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"18","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"45% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"11 poster presentations","order":10,"name":"additional_info_on_review_process","label":"Additional Info on Review Process","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}