{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,19]],"date-time":"2025-12-19T09:43:19Z","timestamp":1766137399594,"version":"3.40.3"},"publisher-location":"Cham","reference-count":14,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030451233"},{"type":"electronic","value":"9783030451240"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-45124-0_9","type":"book-chapter","created":{"date-parts":[[2020,4,28]],"date-time":"2020-04-28T23:22:43Z","timestamp":1588116163000},"page":"101-108","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Automatic Flat-Level Circuit Generation with Genetic Algorithms"],"prefix":"10.1007","author":[{"given":"Miguel","family":"Campilho-Gomes","sequence":"first","affiliation":[]},{"given":"Rui","family":"Tavares","sequence":"additional","affiliation":[]},{"given":"Jo\u00e3o","family":"Goes","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,4,29]]},"reference":[{"issue":"1","key":"9_CR1","first-page":"15","volume":"55","author":"C Farag\u00f3","year":"2014","unstructured":"Farag\u00f3, C., Lodin, A., Groza, R.: An operational transconductance amplifier sizing methodology with genetic algorithm-based optimization. Acta Technica Napocensis. Electronica-Telecomunicatii 55(1), 15\u201320 (2014)","journal-title":"Acta Technica Napocensis. Electronica-Telecomunicatii"},{"key":"9_CR2","unstructured":"ITRS: International Technology Roadmap for Semiconductors, ITRS Web-Site. http:\/\/www.itrs2.net"},{"issue":"1","key":"9_CR3","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1016\/j.vlsi.2010.06.003","volume":"44","author":"C Ferent","year":"2011","unstructured":"Ferent, C., Doboli, A.: Measuring the uniqueness and variety of analog circuit design features. Integr. VLSI J. 44(1), 39\u201350 (2011)","journal-title":"Integr. VLSI J."},{"key":"9_CR4","volume-title":"Adaptation in Natural and Artificial Systems","author":"JH Holland","year":"1975","unstructured":"Holland, J.H.: Adaptation in Natural and Artificial Systems. University of Michigan Press, Ann Arbor (1975). Second Edition, 1992"},{"key":"9_CR5","unstructured":"Lohn, J.D., Colombano, S.P., Haith, G.L., Stassinopoulos, D., Norvig, P.: A parallel genetic algorithm for automated electronic circuit design. In: Proceedings Computational Aerosciences Workshop (2000)"},{"issue":"11","key":"9_CR6","doi-asserted-by":"publisher","first-page":"1032","DOI":"10.4236\/jsea.2010.311121","volume":"3","author":"YA Sapargaliyev","year":"2010","unstructured":"Sapargaliyev, Y.A., Kalganova, T.G.: Challenging the evolutionary strategy for synthesis of analogue computational circuits. J. Softw. Eng. Appl. 3(11), 1032\u20131039 (2010)","journal-title":"J. Softw. Eng. Appl."},{"key":"9_CR7","unstructured":"Zebulum, R.S., Pacheco, M.A., Vellasco, M.: Comparison of different evolutionary methodologies applied to electronic filter design. In: 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence, pp. 434\u2013439. IEEE (1998)"},{"key":"9_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1007\/BFb0057614","volume-title":"Evolvable Systems: From Biology to Hardware","author":"JD Lohn","year":"1998","unstructured":"Lohn, J.D., Colombano, S.P.: Automated analog circuit synthesis using a linear representation. In: Sipper, M., Mange, D., P\u00e9rez-Uribe, A. (eds.) ICES 1998. LNCS, vol. 1478, pp. 125\u2013133. Springer, Heidelberg (1998). https:\/\/doi.org\/10.1007\/BFb0057614"},{"issue":"3","key":"9_CR9","doi-asserted-by":"publisher","first-page":"337","DOI":"10.1007\/s11633-014-0870-x","volume":"12","author":"SN Pawar","year":"2015","unstructured":"Pawar, S.N., Bichkar, R.S.: Genetic algorithm with variable length chromosomes for network intrusion detection. Int. J. Autom. Comput. 12(3), 337\u2013342 (2015)","journal-title":"Int. J. Autom. Comput."},{"key":"9_CR10","doi-asserted-by":"crossref","unstructured":"Ni, J., Wang, K., Huang, H., Wu, L., Luo, C.: Robot path planning based on an improved genetic algorithm with variable length chromosome. In: 2016 12th International Conference Natural Computation, Proceedings of the Fuzzy Systems and Knowledge Discovery (ICNC-FSKD), August 2016, pp. 145\u2013149 (2016)","DOI":"10.1109\/FSKD.2016.7603165"},{"key":"9_CR11","doi-asserted-by":"crossref","unstructured":"Deif, D.S., Gadallah, Y.: Wireless sensor network deployment using a variable-length genetic algorithm. In: Proceedings IEEE Wireless Communications and Networking Conference (WCNC), April 2014, pp. 2450\u20132455 (2014)","DOI":"10.1109\/WCNC.2014.6952773"},{"issue":"1","key":"9_CR12","doi-asserted-by":"publisher","first-page":"118","DOI":"10.1109\/TEVC.2006.878096","volume":"11","author":"B Hutt","year":"2007","unstructured":"Hutt, B., Warwick, K.: Synapsing variable-length crossover: meaningful crossover for variable-length genomes. IEEE Trans. Evol. Comput. 11(1), 118\u2013131 (2007)","journal-title":"IEEE Trans. Evol. Comput."},{"issue":"1","key":"9_CR13","doi-asserted-by":"publisher","first-page":"136","DOI":"10.1016\/j.vlsi.2009.09.001","volume":"43","author":"M Barros","year":"2010","unstructured":"Barros, M., Guilherme, J., Horta, N.: Analog circuits optimization based on evolutionary computation techniques. Integr. VLSI J. 43(1), 136\u2013155 (2010)","journal-title":"Integr. VLSI J."},{"key":"9_CR14","unstructured":"SourceForge: Mixed Mode-Mixed Level Circuit Simulator based on Berkeley\u2019s SPICE 3F5. http:\/\/ngspice.sourceforge.net\/"}],"container-title":["IFIP Advances in Information and Communication Technology","Technological Innovation for Life Improvement"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-45124-0_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,29]],"date-time":"2024-04-29T00:03:02Z","timestamp":1714348982000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-45124-0_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030451233","9783030451240"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-45124-0_9","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"29 April 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DoCEIS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Doctoral Conference on Computing, Electrical and Industrial Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Costa de Caparica","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Portugal","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2020","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1 July 2020","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"3 July 2020","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"doceis2020","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/doceis.dee.fct.unl.pt","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"91","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"20","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"24","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"22% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3.44","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}