{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T18:30:56Z","timestamp":1780511456944,"version":"3.54.1"},"publisher-location":"Cham","reference-count":29,"publisher":"Springer International Publishing","isbn-type":[{"value":"9783030532727","type":"print"},{"value":"9783030532734","type":"electronic"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-53273-4_1","type":"book-chapter","created":{"date-parts":[[2020,7,22]],"date-time":"2020-07-22T09:07:29Z","timestamp":1595408849000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Software-Based Self-Test for Delay Faults"],"prefix":"10.1007","author":[{"given":"Michelangelo","family":"Grosso","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matteo","family":"Sonza Reorda","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Salvatore","family":"Rinaudo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2020,7,22]]},"reference":[{"issue":"3","key":"1_CR1","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/MDT.2010.5","volume":"27","author":"M Psarakis","year":"2010","unstructured":"Psarakis, M., Gizopoulos, D., Sanchez, E., Reorda, M.S.: Microprocessor software-based self-testing. IEEE Des. Test Comput. 27(3), 4\u201319 (2010)","journal-title":"IEEE Des. Test Comput."},{"issue":"3","key":"1_CR2","doi-asserted-by":"publisher","first-page":"744","DOI":"10.1109\/TC.2015.2498546","volume":"65","author":"P Bernardi","year":"2016","unstructured":"Bernardi, P., Cantoro, R., De Luca, S., Sanchez, E., Sansonetti, A.: Development flow for on-line core self-test of automotive microcontrollers. IEEE Trans. Comput. 65(3), 744\u2013754 (2016)","journal-title":"IEEE Trans. Comput."},{"key":"1_CR3","doi-asserted-by":"crossref","unstructured":"Shaheen, A.-U.-R., Hussin, F.A., Hamid, N.H., Ali, N.H.Z.: Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram. In: IEEE International Conference on Intelligent and Advanced Systems (ICIAS), pp. 1\u20135 (2014)","DOI":"10.1109\/ICIAS.2014.6869530"},{"key":"1_CR4","unstructured":"Singh, V., Inoue, M., Saluja, K.K., Fujiwara, H.: Instruction-based delay fault self-testing of processor cores. In: IEEE International Conference on VLSI Design, pp. 933\u2013938 (2004)"},{"key":"1_CR5","doi-asserted-by":"crossref","unstructured":"Hage, N., Gulve, R., Fujita, M., Singh, V.: On testing of superscalar processors in functional mode for delay faults. In: IEEE International Conference on VLSI Design and International Conference on Embedded Systems (VLSID), pp. 397\u2013402 (2017)","DOI":"10.1109\/VLSID.2017.58"},{"issue":"11","key":"1_CR6","doi-asserted-by":"publisher","first-page":"1441","DOI":"10.1109\/TVLSI.2008.2000866","volume":"16","author":"M Psarakis","year":"2008","unstructured":"Psarakis, M., Gizopoulos, D., Hatzimihail, M., Paschalis, A., Raghunathan, A., Ravi, S.: Systematic software-based self-test for pipelined processors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(11), 1441\u20131453 (2008)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"1_CR7","doi-asserted-by":"crossref","unstructured":"Christou, K., Michael, M.K., Bernardi, P., Grosso, M., Sanchez, E., Reorda, M.S.: A novel SBST generation technique for path-delay faults in microprocessors exploiting gate- and rt-level descriptions. In: IEEE VLSI Test Symposium, pp. 389\u2013394 (2008)","DOI":"10.1109\/VTS.2008.37"},{"key":"1_CR8","unstructured":"Wen, C.H.-P., Wang, L.-C., Cheng, K.-T., Yang, K., Liu, W.-T., Chen, J.-J.: On a software-based self-test methodology and its application. In: IEEE VLSI Test Symposium, pp. 107\u2013113 (2005)"},{"issue":"4","key":"1_CR9","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1109\/54.895002","volume":"17","author":"W-C Lai","year":"2000","unstructured":"Lai, W.-C., Krstic, A., Cheng, K.-T.: Functionally testable path delay faults on a microprocessor. IEEE Des. Test Comput. 17(4), 6\u201314 (2000)","journal-title":"IEEE Des. Test Comput."},{"key":"1_CR10","unstructured":"Fukunaga, M., Kajihara, S., Takeoka, S.: On estimation of fault efficiency for path delay faults. In: IEEE Asian Test Symposium, pp. 64\u201367 (2003)"},{"key":"1_CR11","doi-asserted-by":"crossref","unstructured":"Bernardi, P., Grosso, M., Sanchez, E., Reorda, M.S.: A deterministic methodology for identifying functionally untestable path-delay faults in microprocessor cores. In: IEEE International Workshop on Microprocessor Test and Verification, pp. 103\u2013108 (2008)","DOI":"10.1109\/MTV.2008.9"},{"key":"1_CR12","volume-title":"Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits","author":"SK Goel","year":"2017","unstructured":"Goel, S.K., Chakrabarty, K.: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. CRC Press, Boca Raton (2017)"},{"key":"1_CR13","doi-asserted-by":"crossref","unstructured":"Grosso, M., Rinaudo, S., Casalino, A., Reorda, M.S.: Software-based self-test for transition faults: a case study. In: IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 76\u201381 (2019)","DOI":"10.1109\/VLSI-SoC.2019.8920306"},{"key":"1_CR14","unstructured":"Nigh, P., Gattiker, A.: Test method evaluation experiments & data. In: IEEE International Test Conference, pp. 454\u2013463 (2000)"},{"key":"1_CR15","unstructured":"Park, E.S., Mercer, M.R., Williams, T.W.: Statistical delay fault coverage and defect level for delay faults. In: IEEE International Test Conference, pp. 492\u2013499 (1988)"},{"key":"1_CR16","unstructured":"Mattiuzzo, R., Appello, D., Allsup, C.:  Small-delay-defect testing. EDN (Electr. Des. News) 54(13), 28 (2009)"},{"key":"1_CR17","unstructured":"Metzler, C., Todri-Sanial, A., Bosio, A., Dilillo, L., Girard, P., Virazel, A.: Timing-aware ATPG for critical paths with multiple TSVs. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 116\u2013121 (2004)"},{"issue":"2","key":"1_CR18","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1109\/MDT.2011.26","volume":"28","author":"M Yilmaz","year":"2011","unstructured":"Yilmaz, M., Tehranipoor, M., Chakrabarty, K.: A metric to target small-delay defects in industrial circuits. IEEE Des. Test Comput. 28(2), 52\u201361 (2011)","journal-title":"IEEE Des. Test Comput."},{"key":"1_CR19","doi-asserted-by":"crossref","unstructured":"Uzzaman, A., Tegethoff, M., Li, B., Mc Cauley, K., Hamada, S., Sato, Y.: Not all delay tests are the same - SDQL model shows truetime. In: IEEE Asian Test Symposium (ATS), pp. 147\u2013152 (2006)","DOI":"10.1109\/ATS.2006.261013"},{"key":"1_CR20","volume-title":"Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits","author":"M Bushnell","year":"2000","unstructured":"Bushnell, M., Agrawal, V.: Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits. Kluwer Academic Publisher, Dordrecht (2000)"},{"issue":"8","key":"1_CR21","doi-asserted-by":"publisher","first-page":"845","DOI":"10.1109\/43.511566","volume":"15","author":"K-T Cheng","year":"1996","unstructured":"Cheng, K.-T., Chen, H.-C.: Classification and identification of nonrobust untestable path delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), 845\u2013853 (1996)","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"1_CR22","doi-asserted-by":"crossref","unstructured":"Liu, X., Hsiao, M.S.: On identifying functionally untestable transition faults. In: IEEE International High-Level Design Validation and Test Workshop, pp. 121\u2013126 (2004)","DOI":"10.1109\/HLDVT.2004.1431252"},{"key":"1_CR23","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Peng, Z., Jiang, J., Li, H., Fujita, M.: Temperature-aware software-based self-testing for delay faults. In: IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 423\u2013428 (2015)","DOI":"10.7873\/DATE.2015.0744"},{"key":"1_CR24","doi-asserted-by":"crossref","unstructured":"Touati, A., Bosio, A., Girard, P., Virazel, A., Bernardi, P., Reorda, M.S.: Improving the functional test delay fault coverage: a microprocessor case study. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 731\u2013736 (2016)","DOI":"10.1109\/ISVLSI.2016.42"},{"issue":"8","key":"1_CR25","first-page":"1","volume":"26","author":"A Touati","year":"2017","unstructured":"Touati, A., Bosio, A., Girard, P., Virazel, A., Bernardi, P., Reorda, M.S.: Microprocessor testing: functional meets structural test. World Sci. J. Circuits Syst. Comput. 26(8), 1\u201318 (2017)","journal-title":"World Sci. J. Circuits Syst. Comput."},{"key":"1_CR26","doi-asserted-by":"publisher","first-page":"63578","DOI":"10.1109\/ACCESS.2019.2917036","volume":"7","author":"A Floridia","year":"2019","unstructured":"Floridia, A., Sanchez, E., Reorda, M.S.: Fault grading techniques of software test libraries for safety-critical applications. IEEE Access 7, 63578\u201363587 (2019)","journal-title":"IEEE Access"},{"issue":"2","key":"1_CR27","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1109\/MDT.2009.43","volume":"26","author":"A Apostolakis","year":"2009","unstructured":"Apostolakis, A., Gizopoulos, G., Psarakis, M., Ravotto, D., Reorda, M.S.: Test program generation for communication peripherals in processor-based SoC devices. IEEE Des. Test Comput. 26(2), 52\u201363 (2009)","journal-title":"IEEE Des. Test Comput."},{"key":"1_CR28","doi-asserted-by":"crossref","unstructured":"Wang, J., Li, H., Min, Y., Li, X., Liang, H.: Impact of hazards on pattern selection for small delay defects. In: IEEE Pacific Rim International Symposium on Dependable Computing, pp. 49\u201354 (2009)","DOI":"10.1109\/PRDC.2009.17"},{"key":"1_CR29","doi-asserted-by":"crossref","unstructured":"Cantoro, R., Carbonara, S., Floridia, A., Sanchez, E., Reorda, M.S., Mess, J.-G.: An analysis of test solutions for COTS-based systems in space applications. In: IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 59\u201364 (2018)","DOI":"10.1109\/VLSI-SoC.2018.8644846"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: New Technology Enabler"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-53273-4_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,22]],"date-time":"2024-07-22T00:01:56Z","timestamp":1721606516000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-53273-4_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030532727","9783030532734"],"references-count":29,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-53273-4_1","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"value":"1868-4238","type":"print"},{"value":"1868-422X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"22 July 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Cusco","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Peru","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 October 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 October 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/vlsi-soc.pe\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}