{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T12:50:31Z","timestamp":1743079831437,"version":"3.40.3"},"publisher-location":"Cham","reference-count":33,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030532727"},{"type":"electronic","value":"9783030532734"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-53273-4_12","type":"book-chapter","created":{"date-parts":[[2020,7,22]],"date-time":"2020-07-22T09:07:29Z","timestamp":1595408849000},"page":"257-278","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Accelerating Inference on Binary Neural Networks with Digital RRAM Processing"],"prefix":"10.1007","author":[{"given":"Jo\u00e3o","family":"Vieira","sequence":"first","affiliation":[]},{"given":"Edouard","family":"Giacomin","sequence":"additional","affiliation":[]},{"given":"Yasir","family":"Qureshi","sequence":"additional","affiliation":[]},{"given":"Marina","family":"Zapater","sequence":"additional","affiliation":[]},{"given":"Xifan","family":"Tang","sequence":"additional","affiliation":[]},{"given":"Shahar","family":"Kvatinsky","sequence":"additional","affiliation":[]},{"given":"David","family":"Atienza","sequence":"additional","affiliation":[]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,7,22]]},"reference":[{"key":"12_CR1","doi-asserted-by":"crossref","unstructured":"Collobert, R., Weston, J.: A unified architecture for natural language processing: deep neural networks with multitask learning. In: ICML. ACM International Conference Proceeding Series, vol. 307, pp. 160\u2013167. ACM (2008)","DOI":"10.1145\/1390156.1390177"},{"issue":"6419","key":"12_CR2","doi-asserted-by":"publisher","first-page":"1140","DOI":"10.1126\/science.aar6404","volume":"362","author":"D Silver","year":"2018","unstructured":"Silver, D., et al.: A general reinforcement learning algorithm that masters chess, shogi, and go through self-play. Science 362(6419), 1140\u20131144 (2018)","journal-title":"Science"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Redmon, J., Divvala, S.K., Girshick, R.B., Farhadi, A.: You only look once: unified, real-time object detection. In: CVPR, pp. 779\u2013788. IEEE Computer Society (2016)","DOI":"10.1109\/CVPR.2016.91"},{"key":"12_CR4","doi-asserted-by":"crossref","unstructured":"Shafiee, A., et al.: ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In: ISCA, pp. 14\u201326. IEEE Computer Society (2016)","DOI":"10.1145\/3007787.3001139"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Vieira, J., et al.: A product engine for energy-efficient execution of binary neural networks using resistive memories. In: VLSI-SoC, pp. 160\u2013165. IEEE (2019)","DOI":"10.1109\/VLSI-SoC.2019.8920343"},{"key":"12_CR6","doi-asserted-by":"crossref","unstructured":"Giacomin, E., Greenberg-Toledo, T., Kvatinsky, S., Gaillardon, P.: A robust digital RRAM-based convolutional block for low-power image processing and learning applications. IEEE Trans. Circ. Syst. 66-I(2), 643\u2013654 (2019)","DOI":"10.1109\/TCSI.2018.2872455"},{"key":"12_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"525","DOI":"10.1007\/978-3-319-46493-0_32","volume-title":"Computer Vision \u2013 ECCV 2016","author":"M Rastegari","year":"2016","unstructured":"Rastegari, M., Ordonez, V., Redmon, J., Farhadi, A.: XNOR-Net: imagenet classification using binary convolutional neural networks. In: Leibe, B., Matas, J., Sebe, N., Welling, M. (eds.) ECCV 2016. LNCS, vol. 9908, pp. 525\u2013542. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-46493-0_32"},{"key":"12_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"281","DOI":"10.1007\/978-3-319-11179-7_36","volume-title":"Artificial Neural Networks and Machine Learning \u2013 ICANN 2014","author":"J Cong","year":"2014","unstructured":"Cong, J., Xiao, B.: Minimizing computation in convolutional neural networks. In: Wermter, S., et al. (eds.) ICANN 2014. LNCS, vol. 8681, pp. 281\u2013290. Springer, Cham (2014). https:\/\/doi.org\/10.1007\/978-3-319-11179-7_36"},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"Girshick, R.B., Donahue, J., Darrell, T., Malik, J.: Rich feature hierarchies for accurate object detection and semantic segmentation. In: CVPR, pp. 580\u2013587. IEEE Computer Society (2014)","DOI":"10.1109\/CVPR.2014.81"},{"key":"12_CR10","doi-asserted-by":"crossref","unstructured":"Girshick, R.B.: Fast R-CNN. In: ICCV, pp. 1440\u20131448. IEEE Computer Society (2015)","DOI":"10.1109\/ICCV.2015.169"},{"key":"12_CR11","unstructured":"Netzer, Y., Wang, T., Coates, A., Bissacco, A., Wu, B., Ng, A.Y.: Reading digits in natural images with unsupervised feature learning. In: NIPS Workshop on Deep Learning and Unsupervised Feature Learning 2011 (2011)"},{"issue":"6","key":"12_CR12","doi-asserted-by":"publisher","first-page":"1951","DOI":"10.1109\/JPROC.2012.2190369","volume":"100","author":"HP Wong","year":"2012","unstructured":"Wong, H.P., et al.: Metal-oxide RRAM. Proc. IEEE 100(6), 1951\u20131970 (2012)","journal-title":"Proc. IEEE"},{"key":"12_CR13","doi-asserted-by":"crossref","unstructured":"Tang, X., Giacomin, E., Micheli, G.D., Gaillardon, P.: Circuit designs of high-performance and low-power RRAM-based multiplexers based on 4t(ransistor)1r(ram) programming structure. IEEE Trans. Circ. Syst. 64-I(5), 1173\u20131186 (2017)","DOI":"10.1109\/TCSI.2016.2638542"},{"key":"12_CR14","unstructured":"ARM: Arm architecture reference manual (2018)"},{"key":"12_CR15","unstructured":"Redmon, J.: Darknet: Open source neural networks in c (2013\u20132016). http:\/\/pjreddie.com\/darknet\/"},{"issue":"2","key":"12_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"NL Binkert","year":"2011","unstructured":"Binkert, N.L., et al.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1\u20137 (2011)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"12_CR17","doi-asserted-by":"crossref","unstructured":"Butko, A., Garibotti, R., Ost, L., Sassatelli, G.: Accuracy evaluation of GEM5 simulator system. In: ReCoSoC, pp. 1\u20137. IEEE (2012)","DOI":"10.1109\/ReCoSoC.2012.6322869"},{"key":"12_CR18","doi-asserted-by":"crossref","unstructured":"Qureshi, Y.M., Simon, W.A., Zapater, M., Atienza, D., Olcoz, K.: Gem5-x: A gem5-based system level simulation framework to optimize many-core platforms. In: SpringSim, pp. 1\u201312. IEEE (2019)","DOI":"10.23919\/SpringSim.2019.8732862"},{"key":"12_CR19","doi-asserted-by":"crossref","unstructured":"Abouzeid, F., et al.: 30% static power improvement on ARM cortex -a53 using static biasing-anticipation. In: ESSCIRC, pp. 37\u201340. IEEE (2016)","DOI":"10.1109\/ESSCIRC.2016.7598237"},{"key":"12_CR20","doi-asserted-by":"crossref","unstructured":"Pahlevan, A., et al.: Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or not? In: DATE, pp. 147\u2013152. IEEE (2018)","DOI":"10.23919\/DATE.2018.8341994"},{"key":"12_CR21","doi-asserted-by":"crossref","unstructured":"Du, L., et al.: A reconfigurable streaming deep convolutional neural network accelerator for internet of things. IEEE Trans. Circ. Syst. 65-I(1), 198\u2013208 (2018)","DOI":"10.1109\/TCSI.2017.2735490"},{"issue":"1","key":"12_CR22","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1109\/JSSC.2016.2616357","volume":"52","author":"Y Chen","year":"2017","unstructured":"Chen, Y., Krishna, T., Emer, J.S., Sze, V.: Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. J. Solid-State Circuits 52(1), 127\u2013138 (2017)","journal-title":"J. Solid-State Circuits"},{"key":"12_CR23","doi-asserted-by":"crossref","unstructured":"Jo, J., Kim, S., Park, I.: Energy-efficient convolution architecture based on rescheduled dataflow. IEEE Trans. Circ. Syst. 65-I(12), 4196\u20134207 (2018)","DOI":"10.1109\/TCSI.2018.2840092"},{"key":"12_CR24","doi-asserted-by":"crossref","unstructured":"Sim, J., Park, J., Kim, M., Bae, D., Choi, Y., Kim, L.: 14.6 A 1.42tops\/w deep convolutional neural network recognition processor for intelligent IOE systems. In: ISSCC, pp. 264\u2013265. IEEE (2016)","DOI":"10.1109\/ISSCC.2016.7418008"},{"key":"12_CR25","doi-asserted-by":"crossref","unstructured":"Kim, S., Howe, P., Moreau, T., Alaghi, A., Ceze, L., Sathe, V.S.: Energy-efficient neural network acceleration in the presence of bit-level memory errors. IEEE Trans. Circ. Syst. 65-I(12), 4285\u20134298 (2018)","DOI":"10.1109\/TCSI.2018.2839613"},{"key":"12_CR26","first-page":"37","volume":"3","author":"L Ni","year":"2017","unstructured":"Ni, L., Liu, Z., Yu, H., Joshi, R.V.: An energy-efficient digital reram-crossbar-based CNN with bitwise parallelism. IEEE J. Explor. Solid-State Comput. Dev. Circ. 3, 37\u201346 (2017)","journal-title":"IEEE J. Explor. Solid-State Comput. Dev. Circ."},{"key":"12_CR27","doi-asserted-by":"crossref","unstructured":"Tang, T., Xia, L., Li, B., Wang, Y., Yang, H.: Binary convolutional neural network on RRAM. In: ASP-DAC, pp. 782\u2013787. IEEE (2017)","DOI":"10.1109\/ASPDAC.2017.7858419"},{"key":"12_CR28","doi-asserted-by":"crossref","unstructured":"Agbo, I., et al.: Quantification of sense amplifier offset voltage degradation due to zero-and run-time variability. In: ISVLSI, pp. 725\u2013730. IEEE Computer Society (2016)","DOI":"10.1109\/ISVLSI.2016.30"},{"key":"12_CR29","doi-asserted-by":"crossref","unstructured":"Sun, X., Yin, S., Peng, X., Liu, R., Seo, J., Yu, S.: XNOR-RRAM: a scalable and parallel resistive synaptic architecture for binary neural networks. In: DATE, pp. 1423\u20131428. IEEE (2018)","DOI":"10.23919\/DATE.2018.8342235"},{"key":"12_CR30","doi-asserted-by":"crossref","unstructured":"Chen, A., Lin, M.R.: Variability of resistive switching memories and its impact on crossbar array performance. In: 2011 International Reliability Physics Symposium, p. MY-7. IEEE (2011)","DOI":"10.1109\/IRPS.2011.5784590"},{"key":"12_CR31","doi-asserted-by":"crossref","unstructured":"Xia, L., et al.: Switched by input: power efficient structure for RRAM-based convolutional neural network. In: DAC, ACM, pp. 125:1\u2013125:6 (2016)","DOI":"10.1145\/2897937.2898101"},{"key":"12_CR32","doi-asserted-by":"crossref","unstructured":"Chen, X., Jiang, J., Zhu, J., Tsui, C.: A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization. In: ASP-DAC, pp. 123\u2013128. IEEE (2018)","DOI":"10.1109\/ASPDAC.2018.8297293"},{"key":"12_CR33","doi-asserted-by":"crossref","unstructured":"Chi, P., et al.: PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In: ISCA, pp. 27\u201339. IEEE Computer Society (2016)","DOI":"10.1145\/3007787.3001140"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: New Technology Enabler"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-53273-4_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,22]],"date-time":"2024-07-22T00:03:55Z","timestamp":1721606635000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-53273-4_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030532727","9783030532734"],"references-count":33,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-53273-4_12","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"22 July 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Cusco","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Peru","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 October 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 October 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/vlsi-soc.pe\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}