{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,18]],"date-time":"2026-04-18T16:40:16Z","timestamp":1776530416341,"version":"3.51.2"},"publisher-location":"Cham","reference-count":62,"publisher":"Springer International Publishing","isbn-type":[{"value":"9783030532727","type":"print"},{"value":"9783030532734","type":"electronic"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-53273-4_3","type":"book-chapter","created":{"date-parts":[[2020,7,22]],"date-time":"2020-07-22T09:07:29Z","timestamp":1595408849000},"page":"45-68","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Robust FinFET Schmitt Trigger Designs for Low Power Applications"],"prefix":"10.1007","author":[{"given":"Leonardo B.","family":"Moraes","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexandra Lackmann","family":"Zimpeck","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cristina","family":"Meinhardt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,7,22]]},"reference":[{"issue":"7","key":"3_CR1","doi-asserted-by":"publisher","first-page":"1497","DOI":"10.1016\/j.adhoc.2012.02.016","volume":"10","author":"D Miorandi","year":"2012","unstructured":"Miorandi, D., Sicari, S., De Pellegrini, F., Chlamtac, I.: Internet of things: vision, applications and research challenges. Ad Hoc Netw. 10(7), 1497\u20131516 (2012)","journal-title":"Ad Hoc Netw."},{"key":"3_CR2","doi-asserted-by":"crossref","unstructured":"Manoli, Y.: Energy harvesting\u2013from devices to systems. In: 2010 Proceedings of ESSCIRC, pp. 27\u201336. IEEE (2010)","DOI":"10.1109\/ESSCIRC.2010.5619870"},{"key":"#cr-split#-3_CR3.1","unstructured":"Bleitner, A., Goeppert, J., Lotze, N., Keller, M., Manoli, Y.: Comparison and optimization of the minimum supply voltage of schmitt trigger gates versus CMOS gates under process variations. In: ANALOG 2018"},{"key":"#cr-split#-3_CR3.2","unstructured":"16th GMM\/ITG-Symposium, VDE, pp. 1-6 (2018)"},{"key":"3_CR4","doi-asserted-by":"crossref","unstructured":"Abbas, Z., Olivieri, M., Khalid, U., Ripp, A., Pronath, M.: Optimal NBTI degradation and pvt variation resistant device sizing in a full adder cell. In: 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), pp. 1\u20136 (2015)","DOI":"10.1109\/ICRITO.2015.7359366"},{"key":"3_CR5","doi-asserted-by":"crossref","unstructured":"Farkhani, H., Peiravi, A., Kargaard, J.M., Moradi, F.:Comparative study of finFETS versus 22 nm bulk CMOS technologies: SRAM design perspective. In: 2014 27th IEEE International System-on-Chip Conference (SOCC), pp. 449\u2013454. IEEE (2014)","DOI":"10.1109\/SOCC.2014.6948971"},{"key":"3_CR6","doi-asserted-by":"crossref","unstructured":"Zimpeck, A.L., Meinhardt, C., Posser, G., Reis, R.: FinFET cells with different transistor sizing techniques against pvt variations. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 45\u201348 (2016)","DOI":"10.1109\/ISCAS.2016.7527166"},{"key":"3_CR7","doi-asserted-by":"crossref","unstructured":"Nassif, S.: Process variability at the 65 nm node and beyond. In: Custom Integrated Circuits Conference, 2008. CICC 2008, pp. 1\u20138. IEEE (2008)","DOI":"10.1109\/CICC.2008.4672005"},{"key":"3_CR8","doi-asserted-by":"crossref","unstructured":"Hariharan, A.N., Pontarelli, S., Ottavi, M., Lombardi, F.: Modeling open defects in nanometric scale CMOS. In: 2010 IEEE 25th International Symposium on Defect and FaultTolerance in VLSI Systems, pp. 249\u2013257. IEEE (2010)","DOI":"10.1109\/DFT.2010.37"},{"issue":"3","key":"3_CR9","doi-asserted-by":"publisher","first-page":"654","DOI":"10.1109\/TED.2009.2039529","volume":"57","author":"R Vaddi","year":"2010","unstructured":"Vaddi, R., Dasgupta, S., Agarwal, R.: Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS. IEEE Trans. Electron Devices 57(3), 654\u2013664 (2010)","journal-title":"IEEE Trans. Electron Devices"},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"Ames, S.O., Zanandrea, V., Oliveira, I.F.V., Toledo, S.P., Meinhardt, C.: Investigating pvt variability effects on full adders. In: 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 155\u2013161 (2016)","DOI":"10.1109\/PATMOS.2016.7833681"},{"key":"3_CR11","first-page":"6","volume":"2","author":"A Islam","year":"2011","unstructured":"Islam, A., Hasan, M.: Design and analysis of power and variability aware digital summing circuit. ACEEE Int. J. Commun. 2, 6\u201314 (2011)","journal-title":"ACEEE Int. J. Commun."},{"key":"3_CR12","doi-asserted-by":"crossref","unstructured":"Alioto, M., Palumbo, G.: Delay variability due to supply variations in transmission-gate full adders. In: Circuits and Systems, 2007. ISCAS 2007, pp. 3732\u20133735 (2007)","DOI":"10.1109\/ISCAS.2007.378654"},{"issue":"10","key":"3_CR13","doi-asserted-by":"publisher","first-page":"2303","DOI":"10.1109\/JSSC.2007.897148","volume":"42","author":"JP Kulkarni","year":"2007","unstructured":"Kulkarni, J.P., Kim, K., Roy, K.: A 160 mv robust schmitt trigger based subthreshold sram. IEEE J. Solid-State Circ. 42(10), 2303\u20132313 (2007)","journal-title":"IEEE J. Solid-State Circ."},{"key":"3_CR14","unstructured":"Hays, K.I.: A 62 mv 0.13 um CMOS standard-cell-based design technique using schmitt-trigger logic (2012)"},{"key":"3_CR15","doi-asserted-by":"crossref","unstructured":"Melek, L., da Silva, A.L., Schneider, M.C., Galup-Montoro, C.: Analysis and design of the classical CMOS schmitt trigger in subthreshold operation. vol. 64, pp. 869\u2013878. IEEE (2017)","DOI":"10.1109\/TCSI.2016.2631726"},{"issue":"11","key":"3_CR16","first-page":"2920","volume":"64","author":"N Lotze","year":"2017","unstructured":"Lotze, N., Manoli, Y.: Ultra-sub-threshold operation of always-on digital circuits for iot applications by use of schmitt trigger gates. IEEE Trans. Circ. Syst. I: Regular Papers 64(11), 2920\u20132933 (2017)","journal-title":"IEEE Trans. Circ. Syst. I: Regular Papers"},{"key":"3_CR17","doi-asserted-by":"crossref","unstructured":"Dokania, V., Islam, A.: Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells. vol. 9, pp. 204\u2013212. IET (2015)","DOI":"10.1049\/iet-cds.2014.0167"},{"key":"3_CR18","doi-asserted-by":"crossref","unstructured":"Toledo, S.P., Zimpeck, A.L., Reis, R., Meinhardt, C.: Pros and cons of schmitt trigger inverters to mitigate pvt variability on full adders. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1\u20135. IEEE (2018)","DOI":"10.1109\/ISCAS.2018.8351097"},{"key":"3_CR19","doi-asserted-by":"publisher","first-page":"116","DOI":"10.1016\/j.microrel.2018.07.061","volume":"88","author":"LBD Moraes","year":"2018","unstructured":"Moraes, L.B.D., Zimpeck, A., Meinhardt, C., Reis, R.: Evaluation of variability using schmitt trigger on full adders layout. Microelectron. Reliabil. 88, 116\u2013121 (2018)","journal-title":"Microelectron. Reliabil."},{"key":"3_CR20","doi-asserted-by":"crossref","unstructured":"Asenov, A.: Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm mosfets: a statistical 3datomistic\u2019simulation study. vol. 10. IOP Publishing, p. 153 (1999)","DOI":"10.1088\/0957-4484\/10\/2\/309"},{"issue":"45","key":"3_CR21","doi-asserted-by":"publisher","first-page":"433","DOI":"10.1147\/rd.504.0433","volume":"50","author":"K Bernstein","year":"2006","unstructured":"Bernstein, K., et al.: High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50(45), 433\u2013449 (2006)","journal-title":"IBM J. Res. Dev."},{"key":"3_CR22","doi-asserted-by":"crossref","unstructured":"Wang, W., Reddy, V., Yang, B., Balakrishnan, V., Krishnan, S., Cao, Y.: Statistical prediction of circuit aging under process variations. In: 2008 IEEE Custom Integrated Circuits Conference, pp. 13\u201316. IEEE (2008)","DOI":"10.1109\/CICC.2008.4672007"},{"issue":"2","key":"3_CR23","doi-asserted-by":"publisher","first-page":"186","DOI":"10.1109\/24.294986","volume":"43","author":"D Young","year":"1994","unstructured":"Young, D., Christou, A.: Failure mechanism models for electromigration. IEEE Trans. Reliabil. 43(2), 186\u2013192 (1994)","journal-title":"IEEE Trans. Reliabil."},{"issue":"12","key":"3_CR24","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1063\/1.2147714","volume":"98","author":"S Lombardo","year":"2005","unstructured":"Lombardo, S., Stathis, J.H., Linder, B.P., Pey, K.L., Palumbo, F., Tung, C.H.: Dielectric breakdown mechanisms in gate oxides. J. Appl. Phys. 98(12), 12 (2005)","journal-title":"J. Appl. Phys."},{"issue":"4","key":"3_CR25","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1109\/EDL.1983.25667","volume":"4","author":"E Takeda","year":"1983","unstructured":"Takeda, E., Suzuki, N.: An empirical model for device degradation due to hot-carrier injection. IEEE Electron Device Lett. 4(4), 111\u2013113 (1983)","journal-title":"IEEE Electron Device Lett."},{"issue":"1","key":"3_CR26","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/66.554480","volume":"10","author":"BE Stine","year":"1997","unstructured":"Stine, B.E., Boning, D.S., Chung, J.E.: Analysis and decomposition of spatial variation in integrated circuit processes and devices. IEEE Trans. Semiconductor Manuf. 10(1), 24\u201341 (1997)","journal-title":"IEEE Trans. Semiconductor Manuf."},{"key":"3_CR27","unstructured":"Nassif, S.R.: Within-chip variability analysis. In: International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), pp. 283\u2013286. IEEE (1998)"},{"issue":"9","key":"3_CR28","doi-asserted-by":"publisher","first-page":"1837","DOI":"10.1109\/TED.2003.815862","volume":"50","author":"A Asenov","year":"2003","unstructured":"Asenov, A., Brown, A.R., Davies, J.H., Kaya, S., Slavcheva, G.: Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETS. IEEE Trans. Electron Devices 50(9), 1837\u20131852 (2003)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"3","key":"3_CR29","doi-asserted-by":"publisher","first-page":"259","DOI":"10.1109\/5.915374","volume":"89","author":"DJ Frank","year":"2001","unstructured":"Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.S.P.: Device scaling limits of si mosfets and their application dependencies. Proc. IEEE 89(3), 259\u2013288 (2001)","journal-title":"Proc. IEEE"},{"issue":"4","key":"3_CR30","doi-asserted-by":"publisher","first-page":"537","DOI":"10.1109\/5.752515","volume":"87","author":"HS Wong","year":"1999","unstructured":"Wong, H.S., Frank, D.J., Solomon, P.M., Wann, C.H., Welser, J.J.: Nanoscale CMOS. Proc. IEEE 87(4), 537\u2013570 (1999)","journal-title":"Proc. IEEE"},{"key":"3_CR31","unstructured":"Frank, D.J., Wong, H.S.: Simulation of stochastic doping effects in SI MOSFETS. In: 7th International Workshop on Computational Electronics. Book of Abstracts. IWCE (Cat. No. 00EX427), pp. 2\u20133. IEEE (2000)"},{"issue":"6","key":"3_CR32","doi-asserted-by":"publisher","first-page":"2632","DOI":"10.1116\/1.1619954","volume":"21","author":"TA Brunner","year":"2003","unstructured":"Brunner, T.A.: Why optical lithography will live forever. J. Vacuum Sci. Technol. B: Microelectron. Nanometer Structures Process. Measurement Phenomena 21(6), 2632\u20132637 (2003)","journal-title":"J. Vacuum Sci. Technol. B: Microelectron. Nanometer Structures Process. Measurement Phenomena"},{"key":"3_CR33","doi-asserted-by":"crossref","unstructured":"Bhattacharya, D., Jha, N.K.: FinFETS: From devices to architectures. vol. 2014. Hindawi (2014)","DOI":"10.1155\/2014\/365689"},{"key":"3_CR34","volume-title":"Fundamentals of Modern VLSI Devices","author":"Y Taur","year":"2013","unstructured":"Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge (2013)"},{"key":"3_CR35","unstructured":"King, T.J.: FinFETS for nanoscale CMOS digital integrated circuits. In: ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, pp. 207\u2013210, November 2005"},{"issue":"2","key":"3_CR36","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/MDT.2010.50","volume":"27","author":"SK Saha","year":"2010","unstructured":"Saha, S.K.: Modeling process variability in scaled CMOS technology. IEEE Design Test Comput. 27(2), 8\u201316 (2010)","journal-title":"IEEE Design Test Comput."},{"key":"3_CR37","doi-asserted-by":"crossref","unstructured":"Mustafa, M., Bhat, T.A., Beigh, M.: Threshold voltage sensitivity to metal gate work-function based performance evaluation of double-gate n-FINFET structures for LSTP technology (2013)","DOI":"10.4236\/wjnse.2013.31003"},{"issue":"5","key":"3_CR38","doi-asserted-by":"publisher","first-page":"635","DOI":"10.1016\/j.microrel.2010.01.041","volume":"50","author":"CH Hwang","year":"2010","unstructured":"Hwang, C.H., Li, Y., Han, M.H.: Statistical variability in finfet devices with intrinsic parameter fluctuations. Microelectron. Reliabil. 50(5), 635\u2013638 (2010)","journal-title":"Microelectron. Reliabil."},{"key":"3_CR39","doi-asserted-by":"publisher","first-page":"226","DOI":"10.1016\/j.microrel.2017.12.044","volume":"81","author":"S Mukhopadhyay","year":"2018","unstructured":"Mukhopadhyay, S., Lee, Y.H., Lee, J.H.: Time-zero-variability and BTI impact on advanced finfet device and circuit reliability. Microelectron. Reliabil. 81, 226\u2013231 (2018)","journal-title":"Microelectron. Reliabil."},{"issue":"9\u201310","key":"3_CR40","doi-asserted-by":"publisher","first-page":"2319","DOI":"10.1016\/j.microrel.2014.07.023","volume":"54","author":"C Meinhardt","year":"2014","unstructured":"Meinhardt, C., Zimpeck, A.L., Reis, R.A.: Predictive evaluation of electrical characteristics of sub-22 nm finfet technologies under device geometry variations. Microelectron. Reliabil. 54(9\u201310), 2319\u20132324 (2014)","journal-title":"Microelectron. Reliabil."},{"issue":"6","key":"3_CR41","doi-asserted-by":"publisher","first-page":"978","DOI":"10.1109\/TED.2004.829510","volume":"51","author":"CC Hobbs","year":"2004","unstructured":"Hobbs, C.C., et al.: Fermi-level pinning at the polysilicon\/metal-oxide interface-part II. IEEE Trans. Electron Devices 51(6), 978\u2013984 (2004)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"4.5","key":"3_CR42","doi-asserted-by":"publisher","first-page":"387","DOI":"10.1147\/rd.504.0387","volume":"50","author":"EP Gusev","year":"2006","unstructured":"Gusev, E.P., Narayanan, V., Frank, M.M.: Advanced high-$$\\kappa $$ dielectric stacks with polySi and metal gates: recent progress and current challenges. IBM J. Res. Dev. 50(4.5), 387\u2013410 (2006)","journal-title":"IBM J. Res. Dev."},{"key":"3_CR43","unstructured":"Gusev, E., et al.: Ultrathin high-k gate stacks for advanced CMOS devices. In: International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), pp. 20\u201321. IEEE (2001)"},{"key":"3_CR44","unstructured":"Datta, S., et al.: High mobility Si\/SiGe strained channel MOS transistors with HfO\/sub 2\/\/TiN gate stack. In: IEEE International Electron Devices Meeting 2003, pp. 28\u201331. IEEE (2003)"},{"key":"3_CR45","doi-asserted-by":"crossref","unstructured":"Dadgour, H., De, V., Banerjee, K.: Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. In: 2008 IEEE\/ACM International Conference on Computer-Aided Design, pp. 270\u2013277. IEEE (2008)","DOI":"10.1109\/ICCAD.2008.4681585"},{"issue":"11","key":"3_CR46","first-page":"1199","volume":"31","author":"AR Brown","year":"2010","unstructured":"Brown, A.R., Idris, N.M., Watling, J.R., Asenov, A.: Impact of metal gate granularity on threshold voltage variability: a full-scale three-dimensional statistical simulation study. IEEE Electron Device Lett. 31(11), 1199\u20131201 (2010)","journal-title":"IEEE Electron Device Lett."},{"key":"3_CR47","doi-asserted-by":"crossref","unstructured":"Meinhardt, C., Zimpeck, A.L., Reis, R.: Impact of gate workfunction fluctuation on FINFET standard cells. In: 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 574\u2013577 (2014)","DOI":"10.1109\/ICECS.2014.7050050"},{"issue":"2","key":"3_CR48","doi-asserted-by":"publisher","first-page":"224","DOI":"10.1109\/TDMR.2018.2819019","volume":"18","author":"I Pal","year":"2018","unstructured":"Pal, I., Islam, A.: Circuit-level technique to design variation-and noise-aware reliable dynamic logic gates. IEEE Trans. Device Mater. Reliabil. 18(2), 224\u2013239 (2018)","journal-title":"IEEE Trans. Device Mater. Reliabil."},{"issue":"3","key":"3_CR49","doi-asserted-by":"publisher","first-page":"601","DOI":"10.1109\/19.87026","volume":"40","author":"Z Wang","year":"1991","unstructured":"Wang, Z.: CMOS adjustable schmitt triggers. IEEE Trans. Instrumentation Measurement 40(3), 601\u2013605 (1991)","journal-title":"IEEE Trans. Instrumentation Measurement"},{"issue":"4","key":"3_CR50","doi-asserted-by":"publisher","first-page":"203","DOI":"10.1049\/el:19860142","volume":"22","author":"M Steyaert","year":"1986","unstructured":"Steyaert, M., Sansen, W.: Novel CMOS schmitt trigger. Electron. Lett. 22(4), 203\u2013204 (1986)","journal-title":"Electron. Lett."},{"key":"3_CR51","doi-asserted-by":"crossref","unstructured":"Zhang, C., Srivastava, A., Ajmera, P.K.: Low voltage CMOS schmitt trigger circuits. vol. 39, pp. 1696\u20131698 IET (2003)","DOI":"10.1049\/el:20031131"},{"issue":"2","key":"3_CR52","doi-asserted-by":"publisher","first-page":"162","DOI":"10.1109\/4.192048","volume":"28","author":"D Kim","year":"1993","unstructured":"Kim, D., Kih, J., Kim, W.: A new waveform-reshaping circuit: an alternative approach to schmitt trigger. IEEE J. Solid-State Circ. 28(2), 162\u2013164 (1993)","journal-title":"IEEE J. Solid-State Circ."},{"issue":"7","key":"3_CR53","doi-asserted-by":"publisher","first-page":"639","DOI":"10.1049\/el:19920404","volume":"28","author":"A Pfister","year":"1992","unstructured":"Pfister, A.: Novel cmos schmitt trigger with controllable hysteresis. Electron. Lett. 28(7), 639\u2013641 (1992)","journal-title":"Electron. Lett."},{"issue":"18","key":"3_CR54","doi-asserted-by":"publisher","first-page":"1009","DOI":"10.1049\/el:20020687","volume":"38","author":"S Al-Sarawi","year":"2002","unstructured":"Al-Sarawi, S.: Low power schmitt trigger circuit. Electron. Lett. 38(18), 1009\u20131010 (2002)","journal-title":"Electron. Lett."},{"issue":"22","key":"3_CR55","doi-asserted-by":"publisher","first-page":"1213","DOI":"10.1049\/el:20052799","volume":"41","author":"V Pedroni","year":"2005","unstructured":"Pedroni, V.: Low-voltage high-speed schmitt trigger and compact window comparator. Electron. Lett. 41(22), 1213\u20131214 (2005)","journal-title":"Electron. Lett."},{"key":"3_CR56","doi-asserted-by":"publisher","first-page":"197","DOI":"10.1049\/ip-g-1.1984.0037","volume":"131","author":"BL Doki","year":"1984","unstructured":"Doki, B.L.: Cmos schmitt triggers. IEE Proc. G-Electron. Circ. Syst. 131, 197\u2013202 (1984)","journal-title":"IEE Proc. G-Electron. Circ. Syst."},{"key":"3_CR57","doi-asserted-by":"crossref","unstructured":"Clark, L.T., et al.: Asap7: A 7-nm finfet predictive process design kit. vol. 53, Elsevier, pp. 105\u2013115 (2016)","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"3_CR58","doi-asserted-by":"crossref","unstructured":"Alioto, M., Consoli, E., Palumbo, G.: Variations in nanometer CMOS flip-flops part II: energy variability and impact of other sources of variations. IEEE Trans. Circ. Syst. I: Regular Papers, 62, 835\u2013843 (2015)","DOI":"10.1109\/TCSI.2014.2366813"},{"key":"3_CR59","doi-asserted-by":"crossref","unstructured":"Chava, B., et al.: Standard cell design in n7: Euv vs. immersion. In: Design-Process-Technology Co-optimization for Manufacturability IX, vol. 9427, p. 94270E (2015)","DOI":"10.1117\/12.2085739"},{"key":"3_CR60","doi-asserted-by":"crossref","unstructured":"Moraes, L., Zimpeck, A., Meinhardt, C., Reis, R.: Minimum energy finfet schmitt trigger design considering process variability. In: 2019 IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), pp. 88\u201393. IEEE (2019)","DOI":"10.1109\/VLSI-SoC.2019.8920297"},{"key":"3_CR61","unstructured":"The synopsys website. http:\/\/www.synopsys.com"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: New Technology Enabler"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-53273-4_3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,7,22]],"date-time":"2024-07-22T00:02:44Z","timestamp":1721606564000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-53273-4_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030532727","9783030532734"],"references-count":62,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-53273-4_3","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"value":"1868-4238","type":"print"},{"value":"1868-422X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"22 July 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Cusco","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Peru","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 October 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 October 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/vlsi-soc.pe\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}