{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T01:19:06Z","timestamp":1768526346452,"version":"3.49.0"},"publisher-location":"Cham","reference-count":29,"publisher":"Springer International Publishing","isbn-type":[{"value":"9783030609382","type":"print"},{"value":"9783030609399","type":"electronic"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-60939-9_8","type":"book-chapter","created":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T17:22:31Z","timestamp":1602696151000},"page":"110-126","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":16,"title":["DRAMSys4.0: A Fast and Cycle-Accurate SystemC\/TLM-Based DRAM Simulator"],"prefix":"10.1007","author":[{"given":"Lukas","family":"Steiner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthias","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Felipe S.","family":"Prado","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kirill","family":"Bykov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Norbert","family":"Wehn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2020,10,7]]},"reference":[{"key":"8_CR1","doi-asserted-by":"publisher","unstructured":"Sudarshan, C., et al.: A lean, low power, low latency DRAM memory controller for transprecision computing. In: Pnevmatikatos, D.N., Pelcat, M., Jung, M. (eds.) SAMOS 2019. LNCS, vol. 11733, pp. 429\u2013441. Springer, Cham (2019). https:\/\/doi.org\/10.1007\/978-3-030-27562-4_31","DOI":"10.1007\/978-3-030-27562-4_31"},{"key":"8_CR2","doi-asserted-by":"publisher","first-page":"63","DOI":"10.2197\/ipsjtsldm.8.63","volume":"8","author":"M Jung","year":"2015","unstructured":"Jung, M., et al.: DRAMSys: a flexible DRAM subsystem design space exploration framework. IPSJ Trans. Syst. LSI Des. Methodol. 8, 63\u201374 (2015)","journal-title":"IPSJ Trans. Syst. LSI Des. Methodol."},{"issue":"2","key":"8_CR3","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert, N., et al.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1\u20137 (2011)","journal-title":"SIGARCH Comput. Archit. News"},{"issue":"1","key":"8_CR4","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/L-CA.2011.4","volume":"10","author":"P Rosenfeld","year":"2011","unstructured":"Rosenfeld, P., et al.: DRAMSim2: a cycle accurate memory system simulator. Comput. Archit. Lett. 10(1), 16\u201319 (2011)","journal-title":"Comput. Archit. Lett."},{"issue":"2","key":"8_CR5","doi-asserted-by":"crossref","first-page":"106","DOI":"10.1109\/LCA.2020.2973991","volume":"19","author":"S Li","year":"2020","unstructured":"Li, S., et al.: DRAMsim3: a cycle-accurate, thermal-capable DRAM simulator. IEEE Comput. Archit. Lett. 19(2), 106\u2013109 (2020)","journal-title":"IEEE Comput. Archit. Lett."},{"issue":"1","key":"8_CR6","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1109\/LCA.2015.2414456","volume":"15","author":"Y Kim","year":"2015","unstructured":"Kim, Y., et al.: Ramulator: a fast and extensible DRAM simulator. IEEE Comput. Archit. Lett. 15(1), 45\u201349 (2015)","journal-title":"IEEE Comput. Archit. Lett."},{"key":"8_CR7","unstructured":"Jeong, M.K., et al.: DrSim: a platform for flexible DRAM system research. http:\/\/lph.ece.utexas.edu\/public\/DrSim. Accessed 15 Aug 2019"},{"key":"8_CR8","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01724-7","volume-title":"The Memory System: You Can\u2019T Avoid It, You Can\u2019T Ignore It, You Can\u2019T Fake It","author":"B Jacob","year":"2009","unstructured":"Jacob, B.: The Memory System: You Can\u2019T Avoid It, You Can\u2019T Ignore It, You Can\u2019T Fake It. Morgan and Claypool Publishers, San Rafael (2009)"},{"key":"8_CR9","doi-asserted-by":"crossref","unstructured":"Todorov, V., et al.: Automated construction of a cycle-approximate transaction level model of a memory controller. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2012, pp. 1066\u20131071. EDA Consortium, San Jose (2012)","DOI":"10.1109\/DATE.2012.6176653"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"Li, S., et al.: Statistical DRAM modeling. In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, pp. 521\u2013530. Association for Computing Machinery, New York (2019)","DOI":"10.1145\/3357526.3357576"},{"key":"8_CR11","unstructured":"Jung, M., et al.: Fast and accurate DRAM simulation: can we further accelerate it? In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2020, Grenoble, pp. 364\u2013369 (2020)"},{"key":"8_CR12","unstructured":"Yuan, G.L., et al.: A hybrid analytical DRAM performance model (2009)"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"Li, S., et al.: Rethinking cycle accurate DRAM simulation. In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, pp. 184\u2013191. Association for Computing Machinery, New York (2019)","DOI":"10.1145\/3357526.3357539"},{"key":"8_CR14","unstructured":"IEEE Computer Society: IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666\u20132011 (2012)"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"Hansson, A., et al.: Simulating DRAM controllers for future system architecture exploration. In: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 201\u2013210 (2014)","DOI":"10.1109\/ISPASS.2014.6844484"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"Jung, M., et al.: TLM modelling of 3D stacked wide I\/O DRAM subsystems: a virtual platform for memory controller design space exploration. In: Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2013, pp. 5:1\u20135:6. ACM, New York (2013)","DOI":"10.1145\/2432516.2432521"},{"key":"8_CR17","unstructured":"Chandrasekar, K., et al.: DRAMPower: Open-source DRAM power & energy estimation tool. http:\/\/www.drampower.info. Accessed 15 Aug 2019"},{"key":"8_CR18","doi-asserted-by":"crossref","unstructured":"Sridhar, A., et al.: 3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling. In: Proceedings of ICCAD 2010 (2010)","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"8_CR19","unstructured":"MediaBench Consortium. Mediabench (2015). http:\/\/euler.slu.edu\/~fritts\/mediabench\/. Accessed 28 Aug 2015"},{"key":"8_CR20","doi-asserted-by":"crossref","unstructured":"Muhr, H., et al.: Accelerating RTL simulation by several orders of magnitude using clock suppression. In: 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 123\u2013128 (2006)","DOI":"10.1109\/ICSAMOS.2006.300818"},{"key":"8_CR21","doi-asserted-by":"crossref","unstructured":"Jung, M., et al.: Fast validation of DRAM protocols with timed petri nets. In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, pp. 133\u2013147. ACM, New York (2019)","DOI":"10.1145\/3357526.3357556"},{"key":"8_CR22","unstructured":"Petri, C.A.: Kommunikation mit Automaten. PhD thesis, Universit\u00e4t Hamburg (1962)"},{"key":"8_CR23","doi-asserted-by":"crossref","unstructured":"Jung, M., et al.: ConGen: an application specific DRAM memory controller generator. In: Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, pp. 257\u2013267. ACM, New York (2016)","DOI":"10.1145\/2989081.2989131"},{"key":"8_CR24","doi-asserted-by":"crossref","unstructured":"Rixner, S., et al.: Memory access scheduling. In: Proceedings of the 27th Annual International Symposium on Computer Architecture, ISCA 2000, pp. 128\u2013138. ACM, New York (2000)","DOI":"10.1145\/339647.339668"},{"key":"8_CR25","doi-asserted-by":"crossref","unstructured":"Mutlu, O., et al.: Parallelism-aware Batch-scheduling: enhancing both performance and fairness of shared DRAM systems. In: 35th International Symposium on Computer Architecture (ISCA). Association for Computing Machinery Inc. (2008)","DOI":"10.1109\/ISCA.2008.7"},{"key":"8_CR26","doi-asserted-by":"crossref","unstructured":"Ausavarungnirun, R., et al.: Staged memory scheduling: achieving high performance and scalability in heterogeneous systems. In: Proceedings of the 39th Annual International Symposium on Computer Architecture, ISCA 2012, pp. 416\u2013427. IEEE Computer Society, Washington, DC (2012)","DOI":"10.1109\/ISCA.2012.6237036"},{"issue":"4","key":"8_CR27","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1145\/1964218.1964225","volume":"38","author":"AF Rodrigues","year":"2011","unstructured":"Rodrigues, A.F., et al.: The structural simulation toolkit. SIGMETRICS Perform. Eval. Rev. 38(4), 37\u201342 (2011)","journal-title":"SIGMETRICS Perform. Eval. Rev."},{"key":"8_CR28","doi-asserted-by":"publisher","first-page":"475","DOI":"10.1145\/2508148.2485963","volume":"41","author":"D Sanchez","year":"2013","unstructured":"Sanchez, D., et al.: ZSim: fast and accurate microarchitectural simulation of thousand-core systems. ACM SIGARCH Comput. Archit. News 41, 475 (2013)","journal-title":"ACM SIGARCH Comput. Archit. News"},{"issue":"3","key":"8_CR29","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3224419","volume":"2","author":"S Ghose","year":"2018","unstructured":"Ghose, S., et al.: What your DRAM power models are not telling you: lessons from a detailed experimental study. Proc. ACM Meas. Anal. Comput. Syst. 2(3), 1\u201341 (2018)","journal-title":"Proc. ACM Meas. Anal. Comput. Syst."}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-60939-9_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,23]],"date-time":"2022-11-23T08:04:24Z","timestamp":1669190664000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-60939-9_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030609382","9783030609399"],"references-count":29,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-60939-9_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"7 October 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SAMOS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Embedded Computer Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Samos","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Greece","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2020","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"5 July 2020","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 July 2020","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"20","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"samos2020","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/samos-conference.com","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Softconf","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"35","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"25","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"71% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"2","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"The conference was held virtually due to the COVID-19 pandemic.","order":10,"name":"additional_info_on_review_process","label":"Additional Info on Review Process","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}