{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T22:57:50Z","timestamp":1742943470174,"version":"3.40.3"},"publisher-location":"Cham","reference-count":36,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030616373"},{"type":"electronic","value":"9783030616380"}],"license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020]]},"DOI":"10.1007\/978-3-030-61638-0_10","type":"book-chapter","created":{"date-parts":[[2020,10,13]],"date-time":"2020-10-13T23:08:28Z","timestamp":1602630508000},"page":"163-180","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Evolvable Hardware Architectures on FPGA for Side-Channel Security"],"prefix":"10.1007","author":[{"given":"Mansoureh","family":"Labafniya","sequence":"first","affiliation":[]},{"given":"Shahram","family":"Etemadi Borujeni","sequence":"additional","affiliation":[]},{"given":"Nele","family":"Mentens","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,10,14]]},"reference":[{"key":"10_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1007\/3-540-36400-5_4","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2002","author":"D Agrawal","year":"2003","unstructured":"Agrawal, D., Archambeault, B., Rao, J.R., Rohatgi, P.: The EM side\u2014channel(s). In: Kaliski, B.S., Ko\u00e7, K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 29\u201345. Springer, Heidelberg (2003). \nhttps:\/\/doi.org\/10.1007\/3-540-36400-5_4"},{"issue":"6","key":"10_CR2","first-page":"1181","volume":"23","author":"S Asha","year":"2015","unstructured":"Asha, S., Hemamalini, R.R.: Synthesis of adder circuit using cartesian genetic programming. Middle-East J. Sci. Res. 23(6), 1181\u20131186 (2015)","journal-title":"Middle-East J. Sci. Res."},{"key":"10_CR3","doi-asserted-by":"crossref","unstructured":"Babu, K.S., Balaji, N.: Approximation of digital circuits using cartesian genetic programming. In: 2016 International Conference on Communication and Electronics Systems (ICCES), pp. 1\u20136. IEEE (2016)","DOI":"10.1109\/CESYS.2016.7889978"},{"key":"10_CR4","unstructured":"Bao, Z., Watanabe, T.: A new approach for circuit design optimization using genetic algorithm. In: 2008 International SoC Design Conference, vol. 1, pp. I\u2013383. IEEE (2008)"},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"Benkhelifa, E., Pipe, A., Dragffy, G., Nibouche, M.: Towards evolving fault tolerant biologically inspired hardware using evolutionary algorithms. In: 2007 IEEE Congress on Evolutionary Computation, pp. 1548\u20131554. IEEE (2007)","DOI":"10.1109\/CEC.2007.4424657"},{"key":"10_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"450","DOI":"10.1007\/978-3-540-74735-2_31","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2007","author":"A Bogdanov","year":"2007","unstructured":"Bogdanov, A., et al.: PRESENT: an ultra-lightweight block cipher. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 450\u2013466. Springer, Heidelberg (2007). \nhttps:\/\/doi.org\/10.1007\/978-3-540-74735-2_31"},{"key":"10_CR7","unstructured":"Brajer, I., Jakobovi\u0107, D.: Automated design of combinatorial logic circuits. In: 2012 Proceedings of the 35th International Convention MIPRO, pp. 823\u2013828. IEEE (2012)"},{"key":"10_CR8","unstructured":"Dechev, D., Ashraf, R., Luna, F., DeMara, R.: Designing digital circuits for FPGAS using parallel genetic algorithms. Technical report, Sandia National Lab. (SNL-NM), Albuquerque, NM (United States) (2012)"},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"Glette, K.: Design and implementation of scalable online evolvable hardware pattern recognition systems (2008)","DOI":"10.1007\/978-3-642-01636-3_3"},{"key":"10_CR10","unstructured":"Golonek, T., Grzechca, D., Rutkowski, J.: Application of genetic programming to edge detector design. In: 2006 IEEE International Symposium on Circuits and Systems, 4 p. IEEE (2006)"},{"key":"10_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1007\/978-3-642-23951-9_3","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2011","author":"T G\u00fcneysu","year":"2011","unstructured":"G\u00fcneysu, T., Moradi, A.: Generic side-channel countermeasures for reconfigurable devices. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 33\u201348. Springer, Heidelberg (2011). \nhttps:\/\/doi.org\/10.1007\/978-3-642-23951-9_3"},{"key":"10_CR12","doi-asserted-by":"crossref","unstructured":"Hadjam, F.Z., Moraga, C., Benmohamed, M.: Cluster-based evolutionary design of digital circuits using all improved multi-expression programming. In: Proceedings of the 9th Annual Conference companion on Genetic and Evolutionary Computation, pp. 2475\u20132482. ACM (2007)","DOI":"10.1145\/1274000.1274013"},{"issue":"2","key":"10_CR13","first-page":"103","volume":"14","author":"FZ Hadjam","year":"2007","unstructured":"Hadjam, F.Z., Moraga, C., Rahmouni, M.K.: Evolutionary design of digital circuits using improved multi expression programming (IMEP). Mathware Soft Comput. 14(2), 103\u2013123 (2007)","journal-title":"Mathware Soft Comput."},{"key":"10_CR14","doi-asserted-by":"crossref","unstructured":"Holland, J.H., et al.: Adaptation in natural and artificial systems: an introductory analysis with applications to biology, control, and artificial intelligence. MIT Press (1992)","DOI":"10.7551\/mitpress\/1090.001.0001"},{"key":"10_CR15","doi-asserted-by":"crossref","unstructured":"Irfan, M., Habib, Q., Hassan, G.M., Yahya, K.M., Hayat, S.: Combinational digital circuit synthesis using cartesian genetic programming from a nand gate template. In: 2010 6th International Conference on Emerging Technologies (ICET), pp. 343\u2013347. IEEE (2010)","DOI":"10.1109\/ICET.2010.5638462"},{"issue":"5","key":"10_CR16","doi-asserted-by":"publisher","first-page":"88","DOI":"10.25103\/jestr.095.13","volume":"9","author":"S Kazarlis","year":"2016","unstructured":"Kazarlis, S., Kalomiros, J., Kalaitzis, V.: A cartesian genetic programming approach for evolving optimal digital circuits. J. Eng. Sci. Technol. Rev. 9(5), 88\u201392 (2016)","journal-title":"J. Eng. Sci. Technol. Rev."},{"key":"10_CR17","unstructured":"Keller, R.E., Banzhaf, W.: The evolution of genetic code in genetic programming. In: Proceedings of the 1st Annual Conference on Genetic and Evolutionary Computation-Volume 2, pp. 1077\u20131082. Morgan Kaufmann Publishers Inc. (1999)"},{"key":"10_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1007\/978-3-642-15031-9_2","volume-title":"Cryptographic Hardware and Embedded Systems, CHES 2010","author":"L Knudsen","year":"2010","unstructured":"Knudsen, L., Leander, G., Poschmann, A., Robshaw, M.J.B.: PRINTcipher: a block cipher for IC-printing. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 16\u201332. Springer, Heidelberg (2010). \nhttps:\/\/doi.org\/10.1007\/978-3-642-15031-9_2"},{"key":"10_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","volume-title":"Advances in Cryptology \u2014 CRYPTO 99","author":"P Kocher","year":"1999","unstructured":"Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388\u2013397. Springer, Heidelberg (1999). \nhttps:\/\/doi.org\/10.1007\/3-540-48405-1_25"},{"key":"10_CR20","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"104","DOI":"10.1007\/3-540-68697-5_9","volume-title":"Advances in Cryptology \u2014 CRYPTO \u201996","author":"PC Kocher","year":"1996","unstructured":"Kocher, P.C.: Timing attacks on implementations of diffie-Hellman, RSA, DSS, and other systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104\u2013113. Springer, Heidelberg (1996). \nhttps:\/\/doi.org\/10.1007\/3-540-68697-5_9"},{"key":"10_CR21","unstructured":"Koza, J.R.: Genetic programming (1994)"},{"key":"10_CR22","doi-asserted-by":"crossref","unstructured":"L\u00f3pez, B., Valverde, J., de la Torre, E., Riesgo, T.: Power-aware multi-objective evolvable hardware system on an FPGA. In: 2014 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 61\u201368. IEEE (2014)","DOI":"10.1109\/AHS.2014.6880159"},{"key":"10_CR23","volume-title":"Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)","author":"S Mangard","year":"2007","unstructured":"Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security). Springer-Verlag, New York Inc, Secaucus, NJ, USA (2007)"},{"key":"10_CR24","doi-asserted-by":"crossref","unstructured":"Miller, J.F., Harding, S.L.: Cartesian genetic programming. In: Proceedings of the 10th Annual Conference Companion on Genetic and Evolutionary Computation, pp. 2701\u20132726. ACM (2008)","DOI":"10.1145\/1388969.1389075"},{"key":"10_CR25","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"613","DOI":"10.1007\/978-3-319-45823-6_57","volume-title":"Parallel Problem Solving from Nature \u2013 PPSN XIV","author":"S Picek","year":"2016","unstructured":"Picek, S., Sisejkovic, D., Rozic, V., Yang, B., Jakobovic, D., Mentens, N.: Evolving cryptographic pseudorandom number generators. In: Handl, J., Hart, E., Lewis, P.R., L\u00f3pez-Ib\u00e1\u00f1ez, M., Ochoa, G., Paechter, B. (eds.) PPSN 2016. LNCS, vol. 9921, pp. 613\u2013622. Springer, Cham (2016). \nhttps:\/\/doi.org\/10.1007\/978-3-319-45823-6_57"},{"key":"10_CR26","doi-asserted-by":"crossref","unstructured":"Picek, S., et al.: Prngs masking applications and their mapping to evolvable hardware. In: International Conference on Smart Card Research and Advanced Applications, pp. 209\u2013227. Springer (2016)","DOI":"10.1007\/978-3-319-54669-8_13"},{"key":"10_CR27","doi-asserted-by":"crossref","unstructured":"Salvador, R., Otero, A., Mora, J., de la Torre, E., Riesgo, T., Sekanina, L.: Implementation techniques for evolvable HW systems: Virtual vs. dynamic reconfiguration. In: 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 547\u2013550. IEEE (2012)","DOI":"10.1109\/FPL.2012.6339376"},{"issue":"8","key":"10_CR28","doi-asserted-by":"publisher","first-page":"1481","DOI":"10.1109\/TC.2013.78","volume":"62","author":"R Salvador","year":"2013","unstructured":"Salvador, R., Otero, A., Mora, J., de la Torre, E., Riesgo, T., Sekanina, L.: Self-reconfigurable evolvable hardware system for adaptive image processing. IEEE Trans. Comput. 62(8), 1481\u20131493 (2013)","journal-title":"IEEE Trans. Comput."},{"key":"10_CR29","doi-asserted-by":"crossref","unstructured":"Sasdrich, P., Moradi, A., Mischke, O., Guneysu, T.: Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAS. In: 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 130\u2013136. IEEE (2015)","DOI":"10.1109\/HST.2015.7140251"},{"issue":"5\u20136","key":"10_CR30","first-page":"461","volume":"23","author":"L Sekanina","year":"2012","unstructured":"Sekanina, L., Friedl, \u0160.: An evolvable combinational unit for fpgas. Comput. Inform. 23(5\u20136), 461\u2013486 (2012)","journal-title":"Comput. Inform."},{"key":"10_CR31","doi-asserted-by":"publisher","first-page":"175","DOI":"10.1007\/978-3-319-99322-5_9","volume-title":"Approximate Circuits","author":"L Sekanina","year":"2019","unstructured":"Sekanina, L., Vasicek, Z., Mrazek, V.: Automated search-based functional approximation for digital circuits. In: Reda, S., Shafique, M. (eds.) Approximate Circuits, pp. 175\u2013203. Springer, Cham (2019). \nhttps:\/\/doi.org\/10.1007\/978-3-319-99322-5_9"},{"key":"10_CR32","doi-asserted-by":"crossref","unstructured":"Sharma, P., Sasamal, T.N.: Minimization of digital combinational circuit using genetic programming with modified fitness function. In: 2016 2nd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT), pp. 406\u2013410. IEEE (2016)","DOI":"10.1109\/ICATCCT.2016.7912032"},{"key":"10_CR33","doi-asserted-by":"crossref","unstructured":"da Silva, J.E., Bernardino, H.: Cartesian genetic programming with crossover for designing combinational logic circuits. In: 2018 7th Brazilian Conference on Intelligent Systems (BRACIS), pp. 145\u2013150. IEEE (2018)","DOI":"10.1109\/BRACIS.2018.00033"},{"key":"10_CR34","doi-asserted-by":"crossref","unstructured":"Srivastava, A.K., Gupta, A., Chaturvedi, S., Rastogi, V.: Design and simulation of virtual reconfigurable circuit for a fault tolerant system. In: International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), pp. 1\u20134. IEEE (2014)","DOI":"10.1109\/ICRAIE.2014.6909277"},{"key":"10_CR35","doi-asserted-by":"publisher","first-page":"314","DOI":"10.1016\/j.asoc.2013.12.014","volume":"18","author":"A Swarnalatha","year":"2014","unstructured":"Swarnalatha, A., Shanthi, A.: Complete hardware evolution based sopc for evolvable hardware. Appl. Soft Comput. 18, 314\u2013322 (2014)","journal-title":"Appl. Soft Comput."},{"key":"10_CR36","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1007\/978-3-540-74626-3_3","volume-title":"Evolvable Systems: From Biology to Hardware","author":"J Wang","year":"2007","unstructured":"Wang, J., Piao, C.H., Lee, C.H.: Implementing Multi-VRC cores to evolve combinational logic circuits in parallel. In: Kang, L., Liu, Y., Zeng, S. (eds.) ICES 2007. LNCS, vol. 4684, pp. 23\u201334. Springer, Heidelberg (2007). \nhttps:\/\/doi.org\/10.1007\/978-3-540-74626-3_3"}],"container-title":["Lecture Notes in Computer Science","Applied Cryptography and Network Security Workshops"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-61638-0_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,13]],"date-time":"2020-10-13T23:21:54Z","timestamp":1602631314000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-61638-0_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"ISBN":["9783030616373","9783030616380"],"references-count":36,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-61638-0_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2020]]},"assertion":[{"value":"14 October 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ACNS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Applied Cryptography and Network Security","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Rome","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Italy","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2020","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"19 October 2020","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"22 October 2020","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"18","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"acns2020","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/sites.google.com\/di.uniroma1.it\/ACNS2020","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"214","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"46","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"21% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3.7","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"10","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Due to the Corona pandemic the conference was held virtually.","order":10,"name":"additional_info_on_review_process","label":"Additional Info on Review Process","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}