{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,14]],"date-time":"2025-12-14T16:13:38Z","timestamp":1765728818656,"version":"3.40.3"},"publisher-location":"Cham","reference-count":36,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030808242"},{"type":"electronic","value":"9783030808259"}],"license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021]]},"DOI":"10.1007\/978-3-030-80825-9_14","type":"book-chapter","created":{"date-parts":[[2021,7,8]],"date-time":"2021-07-08T23:38:40Z","timestamp":1625787520000},"page":"278-298","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Calibration Done Right: Noiseless Flush+Flush Attacks"],"prefix":"10.1007","author":[{"given":"Guillaume","family":"Didier","sequence":"first","affiliation":[]},{"given":"Cl\u00e9mentine","family":"Maurice","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,7,9]]},"reference":[{"key":"14_CR1","unstructured":"Coffee Lake - Microarchitectures - Intel - WikiChip (2020). https:\/\/en.wikichip.org\/w\/index.php?title=intel\/microarchitectures\/coffee_lake&oldid=97412#Octa-Core. Last edited 3 July 2020"},{"key":"14_CR2","doi-asserted-by":"crossref","unstructured":"Acii\u00e7mez, O., Ko\u00e7, \u00c7.K.: Trace-driven cache attacks on AES (short paper). In: Information and Communications Security, ICICS (2006)","DOI":"10.1007\/11935308_9"},{"key":"14_CR3","doi-asserted-by":"crossref","unstructured":"Amdahl, G.M.: Validity of the single processor approach to achieving large scale computing capabilities. In: Proceedings of the 18\u201320 April 1967, Spring Joint Computer Conference, p. 483\u2013485. AFIPS 1967 (Spring). ACM (1967)","DOI":"10.1145\/1465482.1465560"},{"key":"14_CR4","unstructured":"Apecechea, G.I., Inci, M.S., Eisenbarth, T., Sunar, B.: Fine grain cross-VM attacks on Xen and VMware are possible! IACR Cryptol. ePrint Arch. 2014, 248 (2014). http:\/\/eprint.iacr.org\/2014\/248"},{"key":"14_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"299","DOI":"10.1007\/978-3-319-11379-1_15","volume-title":"Research in Attacks, Intrusions and Defenses","author":"G Irazoqui","year":"2014","unstructured":"Irazoqui, G., Inci, M.S., Eisenbarth, T., Sunar, B.: Wait a minute! A fast, cross-VM attack on AES. In: Stavrou, A., Bos, H., Portokalidis, G. (eds.) RAID 2014. LNCS, vol. 8688, pp. 299\u2013319. Springer, Cham (2014). https:\/\/doi.org\/10.1007\/978-3-319-11379-1_15"},{"key":"14_CR6","unstructured":"Bernstein, D.J.: Cache-timing attacks on AES (2005)"},{"key":"14_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"235","DOI":"10.1007\/978-3-642-11925-5_17","volume-title":"Topics in Cryptology - CT-RSA 2010","author":"A Bogdanov","year":"2010","unstructured":"Bogdanov, A., Eisenbarth, T., Paar, C., Wienecke, M.: Differential cache-collision timing attacks on AES with applications to embedded CPUs. In: Pieprzyk, J. (ed.) CT-RSA 2010. LNCS, vol. 5985, pp. 235\u2013251. Springer, Heidelberg (2010). https:\/\/doi.org\/10.1007\/978-3-642-11925-5_17"},{"key":"14_CR8","unstructured":"Briongos, S., Malag\u00f3n, P., Moya, J.M., Eisenbarth, T.: RELOAD+REFRESH: abusing cache replacement policies to perform stealthy cache attacks. In: USENIX Security Symposium (2020)"},{"key":"14_CR9","doi-asserted-by":"crossref","unstructured":"Canella, C., et al.: Fallout: leaking data on meltdown-resistant CPUs. In: CCS (2019)","DOI":"10.1145\/3319535.3363219"},{"key":"14_CR10","doi-asserted-by":"crossref","unstructured":"Gruss, D., Maurice, C., Wagner, K., Mangard, S.: Flush+flush: a fast and stealthy cache attack. In: DIMVA (2016)","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"14_CR11","unstructured":"Gruss, D., Spreitzer, R., Mangard, S.: Cache template attacks: automating attacks on inclusive last-level caches. In: USENIX Security Symposium (2015)"},{"key":"14_CR12","doi-asserted-by":"crossref","unstructured":"Gullasch, D., Bangerter, E., Krenn, S.: Cache games - bringing access-based cache attacks on AES to practice. In: S&P (2011)","DOI":"10.1109\/SP.2011.22"},{"key":"14_CR13","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach, 6th edn. Morgan Kaufmann (2019)"},{"key":"14_CR14","unstructured":"Intel Corporation: Intel 64 and IA-32 Architectures Optimization Reference Manual (2018). https:\/\/software.intel.com\/sites\/default\/files\/managed\/9e\/bc\/64-ia-32-architectures-optimization-manual.pdf"},{"key":"14_CR15","doi-asserted-by":"crossref","unstructured":"Kocher, P., et al.: Spectre attacks: exploiting speculative execution. In: S&P (2019)","DOI":"10.1109\/SP.2019.00002"},{"key":"14_CR16","unstructured":"Koeune, F., Koeune, F., Quisquater, J.J., Jacques Quisquater, J.: A timing attack against rijndael. Technical report (1999)"},{"key":"14_CR17","unstructured":"Lipp, M., et al.: Meltdown: reading kernel memory from user space. In: USENIX Security (2018)"},{"key":"14_CR18","doi-asserted-by":"crossref","unstructured":"Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-level cache side-channel attacks are practical. In: S&P (2015)","DOI":"10.1109\/SP.2015.43"},{"key":"14_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1007\/978-3-319-20550-2_3","volume-title":"Detection of Intrusions and Malware, and Vulnerability Assessment","author":"C Maurice","year":"2015","unstructured":"Maurice, C., Neumann, C., Heen, O., Francillon, A.: C5: cross-cores cache covert channel. In: Almgren, M., Gulisano, V., Maggi, F. (eds.) DIMVA 2015. LNCS, vol. 9148, pp. 46\u201364. Springer, Cham (2015). https:\/\/doi.org\/10.1007\/978-3-319-20550-2_3"},{"key":"14_CR20","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1007\/978-3-319-26362-5_3","volume-title":"Research in Attacks, Intrusions, and Defenses","author":"C Maurice","year":"2015","unstructured":"Maurice, C., Le Scouarnec, N., Neumann, C., Heen, O., Francillon, A.: Reverse engineering intel last-level cache complex addressing using performance counters. In: Bos, H., Monrose, F., Blanc, G. (eds.) RAID 2015. LNCS, vol. 9404, pp. 48\u201365. Springer, Cham (2015). https:\/\/doi.org\/10.1007\/978-3-319-26362-5_3"},{"key":"14_CR21","doi-asserted-by":"crossref","unstructured":"Maurice, C., et al.: Hello from the other side: SSH over robust cache covert channels in the cloud. In: NDSS (2017)","DOI":"10.14722\/ndss.2017.23294"},{"key":"14_CR22","doi-asserted-by":"crossref","unstructured":"Molka, D., Hackenberg, D., Sch\u00f6ne, R., Nagel, W.E.: Cache coherence protocol and memory performance of the intel Haswell-EP architecture. In: 44th International Conference on Parallel Processing, ICPP (2015)","DOI":"10.1109\/ICPP.2015.83"},{"key":"14_CR23","doi-asserted-by":"publisher","unstructured":"Okhravi, H., Bak, S., King, S.T.: Design, implementation and evaluation of covert channel attacks. In: 2010 IEEE International Conference on Technologies for Homeland Security (HST), pp. 481\u2013487 (2010). https:\/\/doi.org\/10.1109\/THS.2010.5654967","DOI":"10.1109\/THS.2010.5654967"},{"key":"14_CR24","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/11605805_1","volume-title":"Topics in Cryptology \u2013 CT-RSA 2006","author":"DA Osvik","year":"2006","unstructured":"Osvik, D.A., Shamir, A., Tromer, E.: Cache attacks and countermeasures: the case of AES. In: Pointcheval, D. (ed.) CT-RSA 2006. LNCS, vol. 3860, pp. 1\u201320. Springer, Heidelberg (2006). https:\/\/doi.org\/10.1007\/11605805_1"},{"key":"14_CR25","unstructured":"Paccagnella, R., Luo, L., Fletcher, C.W.: Lord of the ring(s): side channel attacks on the CPU on-chip ring interconnect are practical. In: S&P (2021)"},{"key":"14_CR26","unstructured":"Percival, C.: Cache missing for fun and profit. In: Proceedings of BSDCan 2005 (2005)"},{"key":"14_CR27","doi-asserted-by":"crossref","unstructured":"Ristenpart, T., Tromer, E., Shacham, H., Savage, S.: Hey, you, get off of my cloud: exploring information leakage in third-party compute clouds. In: CCS (2009)","DOI":"10.1145\/1653662.1653687"},{"key":"14_CR28","unstructured":"Saxena, A., Panda, B.: DABANGG: time for fearless flush based cache attacks. IACR Cryptology ePrint Archive (2020)"},{"key":"14_CR29","doi-asserted-by":"crossref","unstructured":"Vila, P., Ganty, P., Guarnieri, M., K\u00f6pf, B.: CacheQuery: learning replacement policies from hardware caches. In: PLDI (2020)","DOI":"10.1145\/3385412.3386008"},{"key":"14_CR30","doi-asserted-by":"crossref","unstructured":"Vila, P., K\u00f6pf, B., Morales, J.F.: Theory and practice of finding eviction sets. In: S&P (2019)","DOI":"10.1109\/SP.2019.00042"},{"key":"14_CR31","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"314","DOI":"10.1007\/978-3-642-32946-3_23","volume-title":"Financial Cryptography and Data Security","author":"M Wei\u00df","year":"2012","unstructured":"Wei\u00df, M., Heinz, B., Stumpf, F.: A cache timing attack on AES in virtualization environments. In: Keromytis, A.D. (ed.) FC 2012. LNCS, vol. 7397, pp. 314\u2013328. Springer, Heidelberg (2012). https:\/\/doi.org\/10.1007\/978-3-642-32946-3_23"},{"issue":"2","key":"14_CR32","doi-asserted-by":"publisher","first-page":"603","DOI":"10.1109\/TNET.2014.2304439","volume":"23","author":"Z Wu","year":"2015","unstructured":"Wu, Z., Xu, Z., Wang, H.: Whispers in the hyper-space: high-bandwidth and reliable covert channel attacks inside the cloud. IEEE\/ACM Trans. Netw. 23(2), 603\u2013615 (2015)","journal-title":"IEEE\/ACM Trans. Netw."},{"key":"14_CR33","doi-asserted-by":"crossref","unstructured":"Xu, Y., Bailey, M., Jahanian, F., Joshi, K.R., Hiltunen, M.A., Schlichting, R.D.: An exploration of L2 cache covert channels in virtualized environments. In: Cloud Computing Security Workshop, CCSW, pp. 29\u201340. ACM (2011)","DOI":"10.1145\/2046660.2046670"},{"key":"14_CR34","doi-asserted-by":"crossref","unstructured":"Yan, M., Sprabery, R., Gopireddy, B., Fletcher, C.W., Campbell, R.H., Torrellas, J.: Attack directories, not caches: side channel attacks in a non-inclusive world. In: S&P (2019)","DOI":"10.1109\/SP.2019.00004"},{"key":"14_CR35","unstructured":"Yarom, Y., Falkner, K.: FLUSH+RELOAD: a high resolution, low noise, L3 cache side-channel attack. In: USENIX Security Symposium (2014)"},{"key":"14_CR36","unstructured":"Yarom, Y., Ge, Q., Liu, F., Lee, R.B., Heiser, G.: Mapping the intel last-level cache. IACR Cryptology ePrint Archive (2015)"}],"container-title":["Lecture Notes in Computer Science","Detection of Intrusions and Malware, and Vulnerability Assessment"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-80825-9_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,5]],"date-time":"2021-08-05T09:12:35Z","timestamp":1628154755000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-80825-9_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"ISBN":["9783030808242","9783030808259"],"references-count":36,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-80825-9_14","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2021]]},"assertion":[{"value":"9 July 2021","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DIMVA","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2021","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"14 July 2021","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16 July 2021","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"18","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"dimva2021","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/dimva2021.campus.ciencias.ulisboa.pt\/cfp.html","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"HotCRP","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"65","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"18","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"1","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"28% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"5","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}