{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,13]],"date-time":"2025-07-13T22:40:04Z","timestamp":1752446404698,"version":"3.41.2"},"publisher-location":"Cham","reference-count":25,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030816407"},{"type":"electronic","value":"9783030816414"}],"license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021]]},"DOI":"10.1007\/978-3-030-81641-4_16","type":"book-chapter","created":{"date-parts":[[2021,7,14]],"date-time":"2021-07-14T13:05:01Z","timestamp":1626267901000},"page":"343-361","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory"],"prefix":"10.1007","author":[{"given":"Adi","family":"Eliahu","sequence":"first","affiliation":[]},{"given":"Rotem","family":"Ben-Hur","sequence":"additional","affiliation":[]},{"given":"Ronny","family":"Ronen","sequence":"additional","affiliation":[]},{"given":"Shahar","family":"Kvatinsky","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,7,15]]},"reference":[{"issue":"2","key":"16_CR1","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1109\/MDAT.2016.2573586","volume":"34","author":"A Pedram","year":"2017","unstructured":"Pedram, A., Richardson, S., Horowitz, M., Galal, S., Kvatinsky, S.: Dark memory and accelerator-rich system optimization in the dark silicon era. IEEE Des. Test 34(2), 39\u201350 (2017)","journal-title":"IEEE Des. Test"},{"key":"16_CR2","doi-asserted-by":"crossref","unstructured":"Hamdioui, S., et al.: Memristor for computing: myth or reality? In: DATE, pp. 722\u2013731, March 2017","DOI":"10.23919\/DATE.2017.7927083"},{"key":"16_CR3","doi-asserted-by":"publisher","first-page":"333","DOI":"10.1038\/s41928-018-0092-2","volume":"1","author":"D Ielmini","year":"2018","unstructured":"Ielmini, D., Wong, H.-S.P.: In-memory computing with resistive switching devices. Nat. Electron. 1, 333\u2013343 (2018)","journal-title":"Nat. Electron."},{"key":"16_CR4","doi-asserted-by":"publisher","first-page":"466","DOI":"10.1038\/s41928-018-0115-z","volume":"1","author":"MA Lastras-Monta\u00f1o","year":"2018","unstructured":"Lastras-Monta\u00f1o, M.A., Cheng, K.-T.: Resistive random-access memory based on ratioed memristors. Nat. Electron. 1, 466\u2013472 (2018)","journal-title":"Nat. Electron."},{"key":"16_CR5","doi-asserted-by":"publisher","first-page":"2201","DOI":"10.1109\/JPROC.2010.2070050","volume":"98","author":"HSP Wong","year":"2010","unstructured":"Wong, H.S.P., et al.: Phase change memory. Proc. IEEE 98, 2201\u20132227 (2010)","journal-title":"Proc. IEEE"},{"key":"16_CR6","doi-asserted-by":"crossref","unstructured":"Woods, W., Teuscher, C.: Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars. In: IEEE\/ACM NANOARCH, pp. 103\u2013108, July 2017","DOI":"10.1109\/NANOARCH.2017.8053729"},{"issue":"4","key":"16_CR7","doi-asserted-by":"publisher","first-page":"485","DOI":"10.1109\/JPROC.2020.2976475","volume":"108","author":"L Deng","year":"2020","unstructured":"Deng, L., et al.: Model compression and hardware acceleration for neural networks: a comprehensive survey. Proc. IEEE 108(4), 485\u2013532 (2020)","journal-title":"Proc. IEEE"},{"key":"16_CR8","first-page":"895","volume":"61","author":"S Kvatinsky","year":"2014","unstructured":"Kvatinsky, S., et al.: MAGIC-memristor-aided logic. IEEE TCAS II 61, 895\u2013899 (2014)","journal-title":"IEEE TCAS II"},{"key":"16_CR9","doi-asserted-by":"publisher","first-page":"873","DOI":"10.1038\/nature08940","volume":"464","author":"J Borghetti","year":"2010","unstructured":"Borghetti, J., et al.: \u2018memristive\u2019 switches enable \u2018stateful\u2019 logic operations via material implication. Nature 464, 873\u2013876 (2010)","journal-title":"Nature"},{"key":"16_CR10","unstructured":"Testa, E., et al.: Inversion optimization in majority-inverter graphs. In: NANOARCH, pp. 15\u201320, July 2016"},{"key":"16_CR11","doi-asserted-by":"crossref","unstructured":"Tenace, V., et al.: SAID: a supergate-aided logic synthesis flow for memristive crossbars. In: DATE, pp. 372\u2013377, March 2019","DOI":"10.23919\/DATE.2019.8714939"},{"key":"16_CR12","doi-asserted-by":"crossref","unstructured":"Ben Hur, R., et al.: SIMPLE MAGIC: synthesis and in-memory mapping of logic execution for memristor-aided logic. In: IEEE\/ACM ICCAD, pp. 225\u2013232, November 2017","DOI":"10.1109\/ICCAD.2017.8203782"},{"key":"16_CR13","doi-asserted-by":"crossref","unstructured":"Ben-Hur, R., et al.: SIMPLER MAGIC: synthesis and mapping of in-memory logic executed in a single row to improve throughput. In: IEEE TCAD, July 2019","DOI":"10.36227\/techrxiv.12894899"},{"key":"16_CR14","unstructured":"B\u00fcrger, J., et al.: Digital logic synthesis for memristors. In: Reed-Muller, pp. 31\u201340, January 2013"},{"key":"16_CR15","doi-asserted-by":"publisher","first-page":"305205","DOI":"10.1088\/0957-4484\/23\/30\/305205","volume":"23","author":"E Linn","year":"2012","unstructured":"Linn, E., et al.: Beyond von Neumann - logic operations in passive crossbar arrays alongside memory operations. Nanotechnology 23, 305205 (2012)","journal-title":"Nanotechnology"},{"key":"16_CR16","unstructured":"P6 family of processors hardware developer\u2019s manual. http:\/\/download.intel.com\/design\/PentiumII\/manuals\/24400101.pdf"},{"key":"16_CR17","doi-asserted-by":"crossref","unstructured":"Eliahu, A., et al.: abstractPIM: bridging the gap between processing-in-memory technology and instruction set architecture. In: 2020 IFIP\/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), pp. 28\u201333 (2020)","DOI":"10.1109\/VLSI-SOC46417.2020.9344103"},{"key":"16_CR18","doi-asserted-by":"crossref","unstructured":"Reuben, J., et al.: Memristive logic: a framework for evaluation and comparison. In: PATMOS, pp. 1\u20138, September 2017","DOI":"10.1109\/PATMOS.2017.8106959"},{"key":"16_CR19","doi-asserted-by":"publisher","first-page":"152","DOI":"10.1016\/j.vlsi.2018.10.001","volume":"64","author":"DN Yadav","year":"2019","unstructured":"Yadav, D.N., Thangkhiew, P.L., Datta, K.: Look-ahead mapping of Boolean functions in memristive crossbar array. Integration 64, 152\u2013162 (2019)","journal-title":"Integration"},{"key":"16_CR20","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1016\/j.vlsi.2019.11.014","volume":"71","author":"PL Thangkhiew","year":"2020","unstructured":"Thangkhiew, P.L., Zulehner, A., Wille, R., Datta, K., Sengupta, I.: An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD). Integration 71, 125\u2013133 (2020)","journal-title":"Integration"},{"key":"16_CR21","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1007\/978-3-642-14295-6_5","volume-title":"Computer Aided Verification","author":"R Brayton","year":"2010","unstructured":"Brayton, R., Mishchenko, A.: ABC: an academic industrial-strength verification tool. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 24\u201340. Springer, Heidelberg (2010). https:\/\/doi.org\/10.1007\/978-3-642-14295-6_5"},{"key":"16_CR22","volume-title":"Logic Synthesis Using Synopsys","author":"P Kurup","year":"2011","unstructured":"Kurup, P., et al.: Logic Synthesis Using Synopsys, 2nd edn. Springer, Heidelberg (2011)","edition":"2"},{"key":"16_CR23","unstructured":"Amar\u00f9, L., Gaillardon, P.-E., De Micheli, G.: The EPFL combinational benchmark suite. In: IWLS (2015)"},{"key":"16_CR24","doi-asserted-by":"crossref","unstructured":"Gupta, S., Imani, M., Rosing, T.: FELIX: fast and energy-efficient logic in memory. In: 2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1\u20137 (2018)","DOI":"10.1145\/3240765.3240811"},{"key":"16_CR25","doi-asserted-by":"crossref","unstructured":"Peled, N., et al.: X-MAGIC: enhancing PIM using input overwriting capabilities. In: 2020 IFIP\/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), pp. 64\u201369 (2020)","DOI":"10.1109\/VLSI-SOC46417.2020.9344095"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: Design Trends"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-81641-4_16","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,13]],"date-time":"2025-07-13T22:02:57Z","timestamp":1752444177000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-81641-4_16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"ISBN":["9783030816407","9783030816414"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-81641-4_16","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2021]]},"assertion":[{"value":"15 July 2021","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Salt Lake City, UT","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"USA","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2020","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 October 2020","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 October 2020","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2020","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/vlsisoc2020.eng.utah.edu\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}