{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,8]],"date-time":"2025-07-08T05:15:10Z","timestamp":1751951710457,"version":"3.40.3"},"publisher-location":"Cham","reference-count":64,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030884277"},{"type":"electronic","value":"9783030884284"}],"license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021]]},"DOI":"10.1007\/978-3-030-88428-4_19","type":"book-chapter","created":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T06:03:11Z","timestamp":1633068191000},"page":"370-391","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["SERVAS! Secure Enclaves via RISC-V Authenticryption Shield"],"prefix":"10.1007","author":[{"given":"Stefan","family":"Steinegger","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Schrammel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel","family":"Weiser","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pascal","family":"Nasahl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Mangard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2021,10,2]]},"reference":[{"key":"19_CR1","unstructured":"USENIX Annual Technical Conference, USENIX ATC 2019, Renton, WA, USA, 10\u201312 July 2019 (2019)"},{"key":"19_CR2","unstructured":"28th USENIX Security Symposium, USENIX Security 2019, Santa Clara, CA, USA, 14\u201316 August 2019 (2019)"},{"key":"19_CR3","unstructured":"29th USENIX Security Symposium, USENIX Security 2020, 12\u201314 August 2020 (2020)"},{"key":"19_CR4","unstructured":"ACM\/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, 14\u201318 June 2014 (2014)"},{"key":"19_CR5","unstructured":"Advanced Micro Devices Inc.: AMD secure encrypted virtualization (SEV) (2020). https:\/\/developer.amd.com\/sev\/"},{"key":"19_CR6","unstructured":"Advanced Micro Devices Inc.: AMD SEV-SNP: strengthening VM isolation with integrity protection and more (2020). https:\/\/www.amd.com\/system\/files\/TechDocs\/SEV-SNP-strengthening-vm-isolation-with-integrity-protection-and-more.pdf"},{"key":"19_CR7","doi-asserted-by":"crossref","unstructured":"Anati, I., Gueron, S., Johnson, S., Scarlata, V.: Innovative technology for CPU based attestation and sealing. In: HASP 2013, vol. 13, p. 7 (2013)","DOI":"10.1016\/S1350-4789(13)70193-4"},{"key":"19_CR8","unstructured":"Andzakovic, D.: Extracting BitLocker keys from a TPM (2019). https:\/\/pulsesecurity.co.nz\/articles\/TPM-sniffing"},{"key":"19_CR9","unstructured":"Arm Limited: ARM security technology, building a secure system using TrustZone technology (2009). http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.prd29-genc-009492c\/PRD29-GENC-009492C_trustzone_security_whitepaper.pdf. Ref. no. PRD29-GENC-009492C"},{"key":"19_CR10","unstructured":"Arm Limited: Armv8.5-a memory tagging extension (2020). https:\/\/developer.arm.com\/-\/media\/Arm%20Developer%20Community\/PDF\/Arm_Memory_Tagging_Extension_Whitepaper.pdf"},{"key":"19_CR11","unstructured":"Bahmani, R.: CURE: a security architecture with customizable and resilient enclaves. CoRR abs\/2010.15866 (2020)"},{"key":"19_CR12","unstructured":"Beer, I.: An iOS zero-click radio proximity exploit odyssey (2020). https:\/\/googleprojectzero.blogspot.com\/2020\/12\/an-ios-zero-click-radio-proximity.html"},{"key":"19_CR13","unstructured":"Biondo, A., Conti, M., Davi, L., Frassetto, T., Sadeghi, A.: The guard\u2019s dilemma: efficient code-reuse attacks against Intel SGX. In: USENIX Security 2018, pp. 1213\u20131227 (2018)"},{"key":"19_CR14","unstructured":"Boivie, R.: SecureBlue++: CPU support for secure execution (2020). https:\/\/dominoweb.draco.res.ibm.com\/reports\/rc25287.pdf"},{"key":"19_CR15","doi-asserted-by":"publisher","unstructured":"Bourgeat, T., Lebedev, I.A., Wright, A., Zhang, S., Arvind, Devadas, S.: MI6: secure enclaves in a speculative out-of-order processor. In: MICRO 2019, pp. 42\u201356 (2019). https:\/\/doi.org\/10.1145\/3352460.3358310","DOI":"10.1145\/3352460.3358310"},{"key":"19_CR16","doi-asserted-by":"publisher","unstructured":"Busi, M., et al.: Provably secure isolation for interruptible enclaved execution on small microprocessors. In: CSF 2020, pp. 262\u2013276 (2020). https:\/\/doi.org\/10.1109\/CSF49147.2020.00026","DOI":"10.1109\/CSF49147.2020.00026"},{"key":"19_CR17","first-page":"86","volume":"2016","author":"V Costan","year":"2016","unstructured":"Costan, V., Devadas, S.: Intel SGX explained. IACR Cryptol. ePrint Arch. 2016, 86 (2016)","journal-title":"IACR Cryptol. ePrint Arch."},{"key":"19_CR18","unstructured":"Costan, V., Lebedev, I.A., Devadas, S.: Sanctum: minimal hardware extensions for strong software isolation. In: USENIX Security 2016, pp. 857\u2013874 (2016)"},{"key":"19_CR19","doi-asserted-by":"publisher","unstructured":"Dautenhahn, N., Kasampalis, T., Dietz, W., Criswell, J., Adve, V.S.: Nested kernel: an operating system architecture for intra-kernel privilege separation. In: ASPLOS 2015, pp. 191\u2013206 (2015). https:\/\/doi.org\/10.1145\/2694344.2694386","DOI":"10.1145\/2694344.2694386"},{"key":"19_CR20","unstructured":"Dessouky, G., Frassetto, T., Sadeghi, A.: HybCache: hybrid side-channel-resilient caches for trusted execution environments. In: USENIX Security 2020 [3], pp. 451\u2013468 (2020)"},{"key":"19_CR21","unstructured":"Dobraunig, C., Eichlseder, M., Mendel, F., Schl\u00e4ffer, M.: Ascon v1.2. Submission to the CAESAR Competition (2016). https:\/\/ascon.iaik.tugraz.at\/files\/asconv12.pdf"},{"key":"19_CR22","unstructured":"EEMBC: Coremark (2020). https:\/\/www.eembc.org\/coremark\/"},{"key":"19_CR23","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"289","DOI":"10.1007\/978-3-540-74735-2_20","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2007","author":"R Elbaz","year":"2007","unstructured":"Elbaz, R., Champagne, D., Lee, R.B., Torres, L., Sassatelli, G., Guillemin, P.: TEC-Tree: a low-cost, parallelizable tree for efficient defense against memory replay attacks. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 289\u2013302. Springer, Heidelberg (2007). https:\/\/doi.org\/10.1007\/978-3-540-74735-2_20"},{"key":"19_CR24","unstructured":"Five, H.: MultiZone security for RISC-V (2020). https:\/\/hex-five.com\/multizone-security-sdk\/"},{"key":"19_CR25","doi-asserted-by":"publisher","unstructured":"Francillon, A., Nguyen, Q., Rasmussen, K.B., Tsudik, G.: A minimalist approach to remote attestation. In: DATE 2014, pp. 1\u20136 (2014). https:\/\/doi.org\/10.7873\/DATE.2014.257","DOI":"10.7873\/DATE.2014.257"},{"key":"19_CR26","doi-asserted-by":"publisher","unstructured":"Gjerdrum, A.T., Pettersen, R., Johansen, H.D., Johansen, D.: Performance of trusted computing in cloud infrastructures with Intel SGX. In: CLOSER 2017, pp. 668\u2013675 (2017). https:\/\/doi.org\/10.5220\/0006373706680675","DOI":"10.5220\/0006373706680675"},{"key":"19_CR27","unstructured":"Goodin, D.: Attackers exploit 0-day vulnerability that gives full control of Android phones (2019). https:\/\/arstechnica.com\/information-technology\/2019\/10\/attackers-exploit-0day-vulnerability-that-gives-full-control-of-android-phones\/"},{"key":"19_CR28","doi-asserted-by":"publisher","unstructured":"G\u00f6ttel, C.: Security, performance and energy trade-offs of hardware-assisted memory protection mechanisms. In: SRDS 2018, pp. 133\u2013142 (2018). https:\/\/doi.org\/10.1109\/SRDS.2018.00024","DOI":"10.1109\/SRDS.2018.00024"},{"key":"19_CR29","unstructured":"Halderman, J.A., et al.: Lest we remember: cold boot attacks on encryption keys. In: USENIX Security 2008, pp. 45\u201360 (2008)"},{"key":"19_CR30","unstructured":"Hedayati, M., et al.: Hodor: intra-process isolation for high-throughput data plane libraries. In: USENIX ATC 2019 [1], pp. 489\u2013504 (2019)"},{"key":"19_CR31","unstructured":"Intel Corporation: Intel 64 and IA-32 Architectures Software Developer\u2019s Manual, vol. 3 (3A, 3B & 3C): System Programming Guide (325384) (2016)"},{"key":"19_CR32","unstructured":"Intel Corporation: Intel Architecture Memory Encryption Technologies Specification. Ref: # 336907-002US. Rev: 1.2 (2019)"},{"key":"19_CR33","doi-asserted-by":"publisher","unstructured":"Jang, Y., Lee, J., Lee, S., Kim, T.: SGX-bomb: locking down the processor via rowhammer attack. In: SysTEX 2017, pp. 5:1\u20135:6 (2017). https:\/\/doi.org\/10.1145\/3152701.3152709","DOI":"10.1145\/3152701.3152709"},{"key":"19_CR34","doi-asserted-by":"publisher","unstructured":"Joannou, A., et al.: Efficient tagged memory. In: ICCD 2017, pp. 641\u2013648 (2017). https:\/\/doi.org\/10.1109\/ICCD.2017.112","DOI":"10.1109\/ICCD.2017.112"},{"key":"19_CR35","doi-asserted-by":"publisher","unstructured":"Jomaa, N., Nowak, D., Grimaud, G., Hym, S.: Formal proof of dynamic memory isolation based on MMU. In: TASE 2016, pp. 73\u201380 (2016). https:\/\/doi.org\/10.1109\/TASE.2016.28","DOI":"10.1109\/TASE.2016.28"},{"key":"19_CR36","doi-asserted-by":"publisher","unstructured":"Kim, Y., et al.: Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors. In: ISCA 2014 [2], pp. 361\u2013372. https:\/\/doi.org\/10.1109\/ISCA.2014.6853210","DOI":"10.1109\/ISCA.2014.6853210"},{"key":"19_CR37","doi-asserted-by":"publisher","unstructured":"Koning, K., Chen, X., Bos, H., Giuffrida, C., Athanasopoulos, E.: No need to hide: protecting safe regions on commodity hardware. In: EUROSYS 2017, pp. 437\u2013452 (2017). https:\/\/doi.org\/10.1145\/3064176.3064217","DOI":"10.1145\/3064176.3064217"},{"key":"19_CR38","unstructured":"Kossifidis, N.: Secure boot notes (2020). https:\/\/lists.riscv.org\/g\/tech-tee\/message\/288. E-mail #288 from the tech-teelists.riscv.org group from 2 June 2020"},{"key":"19_CR39","doi-asserted-by":"publisher","unstructured":"Lee, D., Kohlbrenner, D., Shinde, S., Asanovic, K., Song, D.: Keystone: an open framework for architecting trusted execution environments. In: EUROSYS 2020, pp. 38:1\u201338:16 (2020). https:\/\/doi.org\/10.1145\/3342195.3387532","DOI":"10.1145\/3342195.3387532"},{"key":"19_CR40","unstructured":"Lee, J., et al.: Hacking in darkness: return-oriented programming against secure enclaves. In: USENIX Security 2017, pp. 523\u2013539 (2017)"},{"key":"19_CR41","unstructured":"Liljestrand, H., Nyman, T., Wang, K., Perez, C.C., Ekberg, J., Asokan, N.: PAC it up: towards pointer integrity using ARM pointer authentication. In: USENIX Security 2019 [2], pp. 177\u2013194 (2019)"},{"key":"19_CR42","doi-asserted-by":"crossref","unstructured":"McKeen, F., et al.: Intel Software Guard Extensions (Intel SGX) support for dynamic memory management inside an enclave. In: HASP 2016, pp. 1\u20139 (2016)","DOI":"10.1145\/2948618.2954331"},{"key":"19_CR43","doi-asserted-by":"publisher","unstructured":"McKeen, F., et al.: Innovative instructions and software model for isolated execution. In: HASP 2013, p. 10 (2013). https:\/\/doi.org\/10.1145\/2487726.2488368","DOI":"10.1145\/2487726.2488368"},{"key":"19_CR44","unstructured":"McVoy, L.W., Staelin, C.: lmbench: portable tools for performance analysis. In: USENIX ATC 1996, pp. 279\u2013294 (1996)"},{"key":"19_CR45","doi-asserted-by":"publisher","unstructured":"Nasahl, P., Schilling, R., Werner, M., Hoogerbrugge, J., Medwed, M., Mangard, S.: CrypTag: thwarting physical and logical memory vulnerabilities using cryptographically colored memory. In: ASIA CCS 2021: ACM Asia Conference on Computer and Communications Security, Virtual Event, Hong Kong, 7\u201311 June 2021, pp. 200\u2013212 (2021). https:\/\/doi.org\/10.1145\/3433210.3453684","DOI":"10.1145\/3433210.3453684"},{"key":"19_CR46","unstructured":"Pallister, J., Hollis, S.J., Bennett, J.: BEEBS: open benchmarks for energy measurements on embedded platforms. CoRR abs\/1308.5174 (2013)"},{"key":"19_CR47","unstructured":"Park, S., Lee, S., Xu, W., Moon, H., Kim, T.: libmpk: Software abstraction for intel memory protection keys (Intel MPK). In: USENIX ATC 2019 [1], pp. 241\u2013254 (2019)"},{"key":"19_CR48","unstructured":"Roberto-Maria, A.: Memory protection for the ARM architecture (2020). https:\/\/rwc.iacr.org\/2020\/slides\/Avanzi.pdf. Presented at Real World Crypto 2020"},{"key":"19_CR49","unstructured":"Schrammel, D., et al.: Donky: domain keys - efficient in-process isolation for RISC-V and x86. In: USENIX Security 2020 [3], pp. 1677\u20131694 (2020)"},{"key":"19_CR50","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"305","DOI":"10.1007\/3-540-56891-3_24","volume-title":"PARLE \u201993 Parallel Architectures and Languages Europe","author":"A Seznec","year":"1993","unstructured":"Seznec, A., Bodin, F.: Skewed-associative caches. In: Bode, A., Reeve, M., Wolf, G. (eds.) PARLE 1993. LNCS, vol. 694, pp. 305\u2013316. Springer, Heidelberg (1993). https:\/\/doi.org\/10.1007\/3-540-56891-3_24"},{"key":"19_CR51","doi-asserted-by":"crossref","unstructured":"Steinegger, S., Schrammel, D., Weiser, S., Nasahl, P., Mangard, S.: SERVAS! secure enclaves via RISC-V authenticryption shield. CoRR abs\/1802.09085 (2021)","DOI":"10.1007\/978-3-030-88428-4_19"},{"key":"19_CR52","doi-asserted-by":"publisher","unstructured":"Szekeres, L., Payer, M., Wei, T., Song, D.: SoK: eternal war in memory. In: S&P 2013, pp. 48\u201362 (2013). https:\/\/doi.org\/10.1109\/SP.2013.13","DOI":"10.1109\/SP.2013.13"},{"key":"19_CR53","doi-asserted-by":"publisher","unstructured":"Taassori, M., Shafiee, A., Balasubramonian, R.: VAULT: reducing paging overheads in SGX with efficient integrity verification structures. In: ASPLOS 2018, pp. 665\u2013678 (2018). https:\/\/doi.org\/10.1145\/3173162.3177155","DOI":"10.1145\/3173162.3177155"},{"issue":"2","key":"19_CR54","doi-asserted-by":"publisher","first-page":"137","DOI":"10.1007\/s13389-018-0180-2","volume":"9","author":"T Unterluggauer","year":"2018","unstructured":"Unterluggauer, T., Werner, M., Mangard, S.: MEAS: memory encryption and authentication secure against side-channel attacks. J. Cryptogr. Eng. 9(2), 137\u2013158 (2018). https:\/\/doi.org\/10.1007\/s13389-018-0180-2","journal-title":"J. Cryptogr. Eng."},{"key":"19_CR55","unstructured":"Vahldiek-Oberwagner, A., Elnikety, E., Duarte, N.O., Sammler, M., Druschel, P., Garg, D.: ERIM: secure, efficient in-process isolation with protection keys (MPK). In: USENIX Security 2019 [2], pp. 1221\u20131238 (2019)"},{"key":"19_CR56","unstructured":"Waterman, A., Asanovi\u0107, K.: The RISC-V instruction set manual, volume II: privileged architecture, document version 20190608-priv-msu-ratified (2019). https:\/\/riscv.org\/specifications\/privileged-isa\/"},{"key":"19_CR57","doi-asserted-by":"crossref","unstructured":"Weiser, S., Werner, M., Brasser, F., Malenko, M., Mangard, S., Sadeghi, A.: TIMBER-V: tag-isolated memory bringing fine-grained enclaves to RISC-V. In: NDSS 2019 (2019)","DOI":"10.14722\/ndss.2019.23068"},{"key":"19_CR58","unstructured":"Werner, M., Unterluggauer, T., Giner, L., Schwarz, M., Gruss, D., Mangard, S.: ScatterCache: thwarting cache attacks via cache set randomization. In: USENIX Security 2019 [2], pp. 675\u2013692 (2019)"},{"key":"19_CR59","doi-asserted-by":"crossref","unstructured":"Werner, M., Unterluggauer, T., Schilling, R., Schaffenrath, D., Mangard, S.: Transparent memory encryption and authentication. In: FPL 2017, pp. 1\u20136 (2017). https:\/\/doi.org\/10.23919\/FPL.2017.8056797","DOI":"10.23919\/FPL.2017.8056797"},{"key":"19_CR60","doi-asserted-by":"publisher","unstructured":"Wong, M.M., Haj-Yahya, J., Chattopadhyay, A.: SMARTS: secure memory assurance of RISC-V trusted SoC. In: HASP 2018, pp. 6:1\u20136:8 (2018). https:\/\/doi.org\/10.1145\/3214292.3214298","DOI":"10.1145\/3214292.3214298"},{"key":"19_CR61","doi-asserted-by":"publisher","unstructured":"Woodruff, J., et al.: The CHERI capability model: revisiting RISC in an age of risk. In: ISCA 2014 [4], pp. 457\u2013468 (2014). https:\/\/doi.org\/10.1109\/ISCA.2014.6853201","DOI":"10.1109\/ISCA.2014.6853201"},{"key":"19_CR62","unstructured":"Wu, H., Preneel, B.: AEGIS: a fast authenticated encryption algorithm v1.1. Submission to the CAESAR Competition (2016). https:\/\/competitions.cr.yp.to\/round3\/aegisv11.pdf"},{"key":"19_CR63","doi-asserted-by":"publisher","first-page":"2629","DOI":"10.1109\/TVLSI.2019.2926114","volume":"27","author":"F Zaruba","year":"2019","unstructured":"Zaruba, F., Benini, L.: The cost of application-class processing: energy and performance analysis of a Linux-ready 1.7-GHz 64-Bit RISC-V core in 22-nm FDSOI technology. IEEE Trans. Very Large Scale Integr. Syst. 27, 2629\u20132640 (2019). https:\/\/doi.org\/10.1109\/TVLSI.2019.2926114","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"19_CR64","unstructured":"Zeldovich, N., Kannan, H., Dalton, M., Kozyrakis, C.: Hardware enforcement of application security policies using tagged memory. In: OSDI 2008, pp. 225\u2013240 (2008)"}],"container-title":["Lecture Notes in Computer Science","Computer Security \u2013 ESORICS 2021"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-88428-4_19","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,10]],"date-time":"2023-01-10T21:58:30Z","timestamp":1673387910000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-88428-4_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021]]},"ISBN":["9783030884277","9783030884284"],"references-count":64,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-88428-4_19","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2021]]},"assertion":[{"value":"2 October 2021","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ESORICS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Symposium on Research in Computer Security","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Darmstadt","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2021","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 October 2021","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"8 October 2021","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"26","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"esorics2021","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/esorics2021.athene-center.de\/index.php","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"351","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"71","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"20% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3.07","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"6.06","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"The conference was held virtually due to the COVID-19 pandemic.","order":10,"name":"additional_info_on_review_process","label":"Additional Info on Review Process","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}