{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T11:33:25Z","timestamp":1743075205952,"version":"3.40.3"},"publisher-location":"Cham","reference-count":89,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030983468"},{"type":"electronic","value":"9783030983475"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-030-98347-5_10","type":"book-chapter","created":{"date-parts":[[2022,8,22]],"date-time":"2022-08-22T14:04:15Z","timestamp":1661177055000},"page":"233-266","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Test and Reliability of Approximate Hardware"],"prefix":"10.1007","author":[{"given":"Marcello","family":"Traiola","sequence":"first","affiliation":[]},{"given":"Bastien","family":"Deveautour","sequence":"additional","affiliation":[]},{"given":"Alberto","family":"Bosio","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Girard","sequence":"additional","affiliation":[]},{"given":"Arnaud","family":"Virazel","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,3,18]]},"reference":[{"key":"10_CR1","doi-asserted-by":"publisher","unstructured":"Al-Maaitah K, Qiqieh I, Soltan A, Yakovlev A. Configurable-accuracy approximate adder design with light-weight fast convergence error recovery circuit. In: 2017 IEEE Jordan conference on applied electrical engineering and computing technologies (AEECT). 2017. pp. 1\u20136. https:\/\/doi.org\/10.1109\/AEECT.2017.8257753.","DOI":"10.1109\/AEECT.2017.8257753"},{"issue":"4","key":"10_CR2","doi-asserted-by":"publisher","first-page":"375","DOI":"10.1007\/s10836-018-5734-9","volume":"34","author":"L Anghel","year":"2018","unstructured":"Anghel L, Benabdenbi M, Bosio A, Traiola M, Vatajelu EI. Test and reliability in approximate computing. J Electron Test. 2018;34(4):375\u201387. https:\/\/doi.org\/10.1007\/s10836-018-5734-9.","journal-title":"J Electron Test"},{"issue":"4","key":"10_CR3","doi-asserted-by":"publisher","first-page":"488","DOI":"10.1109\/TC.2011.31","volume":"61","author":"NDP Avirneni","year":"2012","unstructured":"Avirneni NDP, Somani A. Low overhead soft error mitigation techniques for high-performance and aggressive designs. IEEE Trans Comput. 2012;61(4):488\u2013501. https:\/\/doi.org\/10.1109\/TC.2011.31","journal-title":"IEEE Trans Comput"},{"key":"10_CR4","unstructured":"Avizienis A, Laprie JC, Randell B. Fundamental concepts of dependability. 2001. http:\/\/www.cs.ncl.ac.uk\/publications\/trs\/papers\/739.pdf."},{"issue":"6","key":"10_CR5","doi-asserted-by":"publisher","first-page":"3480","DOI":"10.1109\/TNS.2004.839173","volume":"51","author":"J Benedetto","year":"2004","unstructured":"Benedetto J, Eaton P, Avery K, Mavis D, Gadlage M, Turflinger T, Dodd P, Vizkelethyd G. Heavy ion-induced digital single-event transients in deep submicron processes. IEEE Trans Nuclear Sci. 2004;51(6):3480\u201385. https:\/\/doi.org\/10.1109\/TNS.2004.839173.","journal-title":"IEEE Trans Nuclear Sci"},{"issue":"12","key":"10_CR6","doi-asserted-by":"publisher","first-page":"5511","DOI":"10.1109\/TIT.2009.2032819","volume":"55","author":"S Borade","year":"2009","unstructured":"Borade S, Nakibog\u030clu B, Zheng L. Unequal error protection: An information-theoretic perspective. IEEE Trans Inf Theory. 2009;55(12):5511\u201339. https:\/\/doi.org\/10.1109\/TIT.2009.2032819","journal-title":"IEEE Trans Inf Theory"},{"key":"10_CR7","doi-asserted-by":"publisher","unstructured":"Bosio A, O\u2019Connor I, Traiola M, Echavarria J, Teich J, Hanif MA, Shafique M, Hamdioui S, Deveautour B, Girard P, Virazel A, Bertels K. Emerging computing devices: Challenges and opportunities for test and reliability*. In: 2021 IEEE European test symposium (ETS). 2021. pp. 1\u201310. https:\/\/doi.org\/10.1109\/ETS50041.2021.9465409.","DOI":"10.1109\/ETS50041.2021.9465409"},{"key":"10_CR8","doi-asserted-by":"publisher","unstructured":"Bottoni C, Coeffic B, Daveau JM, Naviner L, Roche P. Partial triplication of a SPARC-V8 microprocessor using fault injection. In: 2015 IEEE 6th Latin American symposium on circuits systems (LASCAS). 2015. pp. 1\u20134. https:\/\/doi.org\/10.1109\/LASCAS.2015.7250415","DOI":"10.1109\/LASCAS.2015.7250415"},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"Bushnell M, Agrawal, V.: Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. 2000. https:\/\/doi.org\/10.1007\/b117406","DOI":"10.1007\/b117406"},{"key":"10_CR10","doi-asserted-by":"crossref","unstructured":"Castano V, Schagaev I. Resilient computer system design. Cham: Springer International Publishing; 2015. https:\/\/link.springer.com\/book\/10.1007\/978-3-319-15069-7. OCLC: 1194524751.","DOI":"10.1007\/978-3-319-15069-7"},{"key":"10_CR11","doi-asserted-by":"publisher","unstructured":"Chandrasekharan A, Eggersgl\u00fc\u00df S, Gro\u00dfe D, Drechsler R. Approximation-aware testing for approximate circuits. In: 2018 23rd Asia and South Pacific design automation conference (ASP-DAC). 2018. pp. 239\u2013244. https:\/\/doi.org\/10.1109\/ASPDAC.2018.8297312.","DOI":"10.1109\/ASPDAC.2018.8297312"},{"issue":"10","key":"10_CR12","doi-asserted-by":"publisher","first-page":"2065","DOI":"10.1109\/TVLSI.2014.2357756","volume":"23","author":"CC Chen","year":"2015","unstructured":"Chen CC, Milor L. Microprocessor aging analysis and reliability modeling due to back-end wearout mechanisms. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2015;23(10):2065\u201376. https:\/\/doi.org\/10.1109\/TVLSI.2014.2357756.","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"10_CR13","doi-asserted-by":"publisher","unstructured":"Deveautour B, Traiola M, Virazel A, Girard P. QAMR: an approximation-based fully reliable TMR alternative for area overhead reduction. In: 2020 IEEE European test symposium (ETS). 2020. pp. 1\u20136. https:\/\/doi.org\/10.1109\/ETS48528.2020.9131574.","DOI":"10.1109\/ETS48528.2020.9131574"},{"key":"10_CR14","doi-asserted-by":"crossref","unstructured":"Deveautour B, Virazel A, Girard P, Gherman V. On using approximate computing to build an error detection scheme for arithmetic circuits. J Electron Test. 2020;36(1):33\u201346. https:\/\/doi.org\/10.1007\/s10836-020-05858-5. http:\/\/link.springer.com\/10.1007\/s10836-020-05858-5.","DOI":"10.1007\/s10836-020-05858-5"},{"issue":"6","key":"10_CR15","doi-asserted-by":"publisher","first-page":"3278","DOI":"10.1109\/TNS.2004.839172","volume":"51","author":"P Dodd","year":"2004","unstructured":"Dodd P, Shaneyfelt M, Felix J, Schwank J. Production and propagation of single-event transients in high-speed digital logic ICs. IEEE Trans Nuclear Sci. 2004;51(6):3278\u201384. https:\/\/doi.org\/10.1109\/TNS.2004.839172.","journal-title":"IEEE Trans Nuclear Sci"},{"key":"10_CR16","unstructured":"Dubrova E. Fault-tolerant design. New York: Springer; 2013. https:\/\/doi.org\/10.1007\/978-1-4614-2113-9. http:\/\/link.springer.com\/10.1007\/978-1-4614-2113-9."},{"key":"10_CR17","doi-asserted-by":"publisher","unstructured":"Dutta A, Jas A. Combinational logic circuit protection using customized error detecting and correcting codes. In: 9th international symposium on quality electronic design (ISQED 2008). 2008. pp. 68\u201373. https:\/\/doi.org\/10.1109\/ISQED.2008.4479700. ISSN: 1948-3295.","DOI":"10.1109\/ISQED.2008.4479700"},{"issue":"1","key":"10_CR18","doi-asserted-by":"publisher","first-page":"33","DOI":"10.1145\/320954.320957","volume":"6","author":"RD Eldred","year":"1959","unstructured":"Eldred RD. Test routines based on symbolic logical statements. J. ACM. 1959;6(1):33\u201337. https:\/\/doi.org\/10.1145\/320954.320957","journal-title":"J. ACM."},{"key":"10_CR19","doi-asserted-by":"publisher","unstructured":"Ernst D, Kim NS, Das S, Pant S, Rao R, Pham T, Ziesler C, Blaauw D, Austin T, Flautner K, Mudge T. Razor: a low-power pipeline based on circuit-level timing speculation. In: Proceedings. 36th annual IEEE\/ACM international symposium on microarchitecture, 2003. MICRO-36. 2003. pp. 7\u201318. https:\/\/doi.org\/10.1109\/MICRO.2003.1253179.","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"10_CR20","doi-asserted-by":"publisher","unstructured":"Fazeli M, Miremadi S, Ejlali A, Patooghy A. Low energy single event upset\/single event transient-tolerant latch for deep subMicron technologies. IET Comput Digit Techniques. 2009;3(3):289. https:\/\/doi.org\/10.1049\/iet-cdt.2008.0099. https:\/\/digital-library.theiet.org\/content\/journals\/10.1049\/iet-cdt.2008.0099.","DOI":"10.1049\/iet-cdt.2008.0099"},{"key":"10_CR21","doi-asserted-by":"publisher","unstructured":"Fazeli M, Ahmadian SN, Miremadi SG, Asadi H, Tahoori MB. Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs). In: 2011 design, automation test in Europe. 2011. pp. 1\u20136. https:\/\/doi.org\/10.1109\/DATE.2011.5763020. ISSN: 1558-1101.","DOI":"10.1109\/DATE.2011.5763020"},{"issue":"3","key":"10_CR22","doi-asserted-by":"publisher","first-page":"1767","DOI":"10.1109\/TNS.2013.2255624","volume":"60","author":"V Ferlet-Cavrois","year":"2013","unstructured":"Ferlet-Cavrois V, Massengill LW, Gouker P. Single event transients in digital CMOS\u2014a review. IEEE Trans Nuclear Sci. 2013;60(3):1767\u201390. https:\/\/doi.org\/10.1109\/TNS.2013.2255624.","journal-title":"IEEE Trans Nuclear Sci"},{"issue":"9","key":"10_CR23","first-page":"2","volume":"28","author":"RA Frohwerk","year":"1977","unstructured":"Frohwerk RA. Signature analysis: a new digital field service method. Hewlett-Packard Journal. 1977;28(9):2\u20138.","journal-title":"Hewlett-Packard Journal"},{"key":"10_CR24","unstructured":"Fujiwara H. FAN: A fanout-oriented test pattern generation algorithm. In: The IEEE international symposium on circuits and systems (ISCAS). 1985. https:\/\/www.researchgate.net\/publication\/234044505_FAN_A_fanout-oriented_test_pattern_generation_algorithm."},{"key":"10_CR25","doi-asserted-by":"publisher","unstructured":"Gebregiorgis A, Tahoori MB. Test pattern generation for approximate circuits based on Boolean satisfiability. In: 2019 Design, automation test in Europe conference exhibition (DATE). 2019. pp. 1028\u20131033. https:\/\/doi.org\/10.23919\/DATE.2019.8714898.","DOI":"10.23919\/DATE.2019.8714898"},{"key":"10_CR26","doi-asserted-by":"publisher","unstructured":"Gielen G, Wit PD, Maricau E, Loeckx J, Martin-Martinez J, Kaczer B, Groeseneken G, Rodriguez R, Nafria M. Emerging yield and reliability challenges in nanometer CMOS technologies. In: Design, Automation and Test in Europe (DATE). 2008. pp. 1322\u20131327. https:\/\/doi.org\/10.1109\/DATE.2008.4484862.","DOI":"10.1109\/DATE.2008.4484862"},{"key":"10_CR27","unstructured":"G\u00f6essel M, Ocheretny V, Sogomonyan E, Marienfeld D. New methods of concurrent checking, frontiers in electronic testing, vol. 42. Dordrecht: Springer Netherlands; 2008. https:\/\/doi.org\/10.1007\/978-1-4020-8420-1. http:\/\/link.springer.com\/10.1007\/978-1-4020-8420-1."},{"key":"10_CR28","doi-asserted-by":"crossref","unstructured":"Gomes IA, Martins MG, Reis AI, Kastensmidt FL. Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron Reliab. 2015;55(9):2072\u20132076. https:\/\/doi.org\/10.1016\/j.microrel.2015.06.125. https:\/\/www.sciencedirect.com\/science\/article\/pii\/S0026271415300676. Proceedings of the 26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.","DOI":"10.1016\/j.microrel.2015.06.125"},{"key":"10_CR29","doi-asserted-by":"publisher","unstructured":"Gomes IAC, Martins M, Reis A, Kastensmidt FL. Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. In: 2015 16th Latin-American test symposium (LATS). 2015. pp. 1\u20136. https:\/\/doi.org\/10.1109\/LATW.2015.7102522.","DOI":"10.1109\/LATW.2015.7102522"},{"key":"10_CR30","doi-asserted-by":"publisher","unstructured":"Hamdioui S. Electronics and computing in nano-era: The good, the bad and the challenging. In: 2015 10th international conference on design technology of integrated systems in nanoscale era (DTIS). 2015. pp. 1\u20131. https:\/\/doi.org\/10.1109\/DTIS.2015.7127342","DOI":"10.1109\/DTIS.2015.7127342"},{"key":"10_CR31","doi-asserted-by":"publisher","unstructured":"Hareland S, Maiz J, Alavi M, Mistry K, Walsta S, Dai C. Impact of CMOS process scaling and SOI on the soft error rates of logic processes. In: 2001 Symposium on VLSI technology. Digest of technical papers (IEEE Cat. No.01 CH37184). 2001. pp. 73\u201374. https:\/\/doi.org\/10.1109\/VLSIT.2001.934953.","DOI":"10.1109\/VLSIT.2001.934953"},{"key":"10_CR32","doi-asserted-by":"crossref","unstructured":"Heimerdinger W, Weinstock C. A conceptual framework for system fault tolerance. Tech. Rep. CMU\/SEI-92-TR-033, Software Engineering Institute, Carnegie Mellon University, Pittsburgh, PA. 1992. http:\/\/resources.sei.cmu.edu\/library\/asset-view.cfm?AssetID=11747.","DOI":"10.21236\/ADA258467"},{"key":"10_CR33","doi-asserted-by":"publisher","unstructured":"Huang W, Stan MR, Gurumurthi S, Ribando RJ, Skadron K. Interaction of scaling trends in processor architecture and cooling. In: 2010 26th Annual IEEE semiconductor thermal measurement and management symposium (SEMI-THERM). 2010. pp. 198\u2013204. https:\/\/doi.org\/10.1109\/STHERM.2010.5444290.","DOI":"10.1109\/STHERM.2010.5444290"},{"key":"10_CR34","unstructured":"International Roadmap for Devices and Systems (IRDSTM) 2020 Edition - IEEE IRDSTM. https:\/\/irds.ieee.org\/editions\/2020."},{"key":"10_CR35","doi-asserted-by":"crossref","unstructured":"Kahng AB, Kang S. Accuracy-configurable adder for approximate arithmetic designs. In: DAC design automation conference 2012. 2012. pp. 820\u20135. https:\/\/doi.org\/10.1145\/2228360.2228509.","DOI":"10.1145\/2228360.2228509"},{"key":"10_CR36","doi-asserted-by":"crossref","unstructured":"Koren I, Krishna CM. Fault-tolerant systems. San Francisco (CA): Morgan Kaufmann; 2021. https:\/\/doi.org\/10.1016\/C2018-0-02160-X. www.sciencedirect.com\/book\/9780128181058\/fault-tolerant-systems.","DOI":"10.1016\/B978-0-12-818105-8.00014-0"},{"key":"10_CR37","volume-title":"Temperature adaptive and variation tolerant CMOS circuits","author":"R Kumar","year":"2008","unstructured":"Kumar R. Temperature adaptive and variation tolerant CMOS circuits. Madison: University of Wisconsin; 2008."},{"issue":"9","key":"10_CR38","doi-asserted-by":"publisher","first-page":"1760","DOI":"10.1109\/TC.2012.146","volume":"62","author":"J Liang","year":"2013","unstructured":"Liang J, Han J, Lombardi F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans Comput. 2013;62(9):1760\u201371. https:\/\/doi.org\/10.1109\/TC.2012.146","journal-title":"IEEE Trans Comput"},{"key":"10_CR39","doi-asserted-by":"crossref","unstructured":"Lienig, J, Bruemmer, H.: Reliability Analysis. In: Fundamentals of Electronic Systems Design, pp. 45\u201373. Springer International Publishing, Cham (2017). https:\/\/doi.org\/10.1007\/978-3-319-55840-0_4. http:\/\/link.springer.com\/10.1007\/978-3-319-55840-0_4.","DOI":"10.1007\/978-3-319-55840-0_4"},{"issue":"2","key":"10_CR40","doi-asserted-by":"publisher","first-page":"200","DOI":"10.1147\/rd.62.0200","volume":"6","author":"R Lyons","year":"1962","unstructured":"Lyons RE, Vanderkulk W. The use of triple-modular redundancy to improve computer reliability. IBM J Res Devel. 1962;6(2):200\u20139. https:\/\/doi.org\/10.1147\/rd.62.0200.","journal-title":"IBM J Res Devel"},{"key":"10_CR41","doi-asserted-by":"publisher","unstructured":"Maheshwari A, Burleson W, Tessier R. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2004;12(3):299\u2013311. https:\/\/doi.org\/10.1109\/TVLSI.2004.824302. http:\/\/ieeexplore.ieee.org\/document\/1281801\/","DOI":"10.1109\/TVLSI.2004.824302"},{"key":"10_CR42","doi-asserted-by":"publisher","unstructured":"Maniatakos M, Makris Y. Workload-driven selective hardening of control state elements in modern microprocessors. In: 2010 28th VLSI test symposium (VTS). 2010. pp. 159\u201364. https:\/\/doi.org\/10.1109\/VTS.2010.5469589. ISSN: 2375-1053.","DOI":"10.1109\/VTS.2010.5469589"},{"key":"10_CR43","doi-asserted-by":"crossref","unstructured":"Mathew J, Shafik RA, Pradhan DK, editors. Energy-efficient fault-tolerant systems. New York: Springer; 2014. https:\/\/doi.org\/10.1007\/978-1-4614-4193-9. http:\/\/link.springer.com\/10.1007\/978-1-4614-4193-9.","DOI":"10.1007\/978-1-4614-4193-9_1"},{"key":"10_CR44","doi-asserted-by":"publisher","unstructured":"Mehrara M, Attariyan M, Shyam S, Constantinides K, Bertacco V, Austin T. Low-cost protection for SER upsets and silicon defects. In: 2007 Design, automation test in Europe conference exhibition. 2007. pp. 1\u20136. https:\/\/doi.org\/10.1109\/DATE.2007.364449.","DOI":"10.1109\/DATE.2007.364449"},{"key":"10_CR45","doi-asserted-by":"crossref","unstructured":"Mittal S. A survey of techniques for approximate computing. ACM Comput Surv. 2016;48(4):62:1\u201362:33. https:\/\/doi.org\/10.1145\/2893356.","DOI":"10.1145\/2893356"},{"key":"10_CR46","doi-asserted-by":"publisher","unstructured":"Mohanram K, Touba N. Cost-effective approach for reducing soft error failure rate in logic circuits. In: International test conference, 2003. Proceedings. ITC 2003. vol. 1. 2003. pp. 893\u2013901. https:\/\/doi.org\/10.1109\/TEST.2003.1271075. ISSN: 1089-3539.","DOI":"10.1109\/TEST.2003.1271075"},{"key":"10_CR47","doi-asserted-by":"publisher","unstructured":"Mrazek V, Hrbacek R, Vasicek Z, Sekanina L. EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. In: Design, automation test in Europe conference exhibition (DATE). 2017. pp. 258\u201361. https:\/\/doi.org\/10.23919\/DATE.2017.7926993.","DOI":"10.23919\/DATE.2017.7926993"},{"key":"10_CR48","doi-asserted-by":"crossref","unstructured":"Naeimi H, DeHon A. Fault-tolerant sub-lithographic design with rollback recovery. Nanotechnology. 2008;19(11):115708. https:\/\/doi.org\/10.1088\/0957-4484\/19\/11\/115708. https:\/\/iopscience.iop.org\/article\/10.1088\/0957-4484\/19\/11\/115708.","DOI":"10.1088\/0957-4484\/19\/11\/115708"},{"key":"10_CR49","unstructured":"NanGate: Nangate 45nm open cell library. http:\/\/www.nangate.com\/?pageid=2325."},{"key":"10_CR50","doi-asserted-by":"crossref","unstructured":"Neumann Jv. Probabilistic logics and the synthesis of reliable organisms from unreliable components. In: Shannon CE, McCarthy J, editors. Automata studies. (AM-34). 1956. pp. 43\u201398. Princeton University Press. https:\/\/doi.org\/10.1515\/9781400882618-003. https:\/\/www.degruyter.com\/document\/doi\/10.1515\/9781400882618-003\/html.","DOI":"10.1515\/9781400882618-003"},{"key":"10_CR51","doi-asserted-by":"crossref","unstructured":"Oda S, Ferry DK, editors. Nanoscale silicon devices, 0 edn. CRC Press; 2018. https:\/\/doi.org\/10.1201\/b19251. https:\/\/www.taylorfrancis.com\/books\/9781482228687.","DOI":"10.1201\/b19251"},{"key":"10_CR52","doi-asserted-by":"publisher","unstructured":"Pagliarini SN, Naviner LAdB, Naviner JF. Selective hardening methodology for combinational logic. In: 2012 13th Latin American test workshop (LATW). 2012. pp. 1\u20136. https:\/\/doi.org\/10.1109\/LATW.2012.6261262. ISSN: 2373-0862.","DOI":"10.1109\/LATW.2012.6261262"},{"key":"10_CR53","volume-title":"Error-correcting codes","author":"W Peterson","year":"1972","unstructured":"Peterson WW, Weldon EJ. Error-correcting codes, 2nd ed. Cambridge: MIT Press; 1972.","edition":"2"},{"key":"10_CR54","doi-asserted-by":"publisher","unstructured":"Polian I, Reddy SM, Becker B. Scalable calculation of logical masking effects for selective hardening against soft errors. In: 2008 IEEE Computer Society annual symposium on VLSI. 2008. pp. 257\u2013262. https:\/\/doi.org\/10.1109\/ISVLSI.2008.22. ISSN: 2159-3477.","DOI":"10.1109\/ISVLSI.2008.22"},{"key":"10_CR55","doi-asserted-by":"crossref","unstructured":"Rehman S, Prabakaran BS, El-Harouni W, Shafique M, Henkel J. Heterogeneous approximate multipliers: architectures and design methodologies. 2019. pp. 45\u201366. Springer. https:\/\/doi.org\/10.1007\/978-3-319-99322-5_3.","DOI":"10.1007\/978-3-319-99322-5_3"},{"key":"10_CR56","first-page":"1","volume-title":"Safety and reliability of software based systems","author":"J Rushby","year":"1997","unstructured":"Rushby J. Formal methods and their role in the certification of critical systems. In: Shaw R, editor. Safety and reliability of software based systems. London: Springer; 1997. pp. 1\u201342."},{"key":"10_CR57","unstructured":"Sachdev M. Defect oriented testing for CMOS analog and digital circuits, Frontiers in electronic testing. vol. 10. Boston: Springer US; 1999. https:\/\/doi.org\/10.1007\/978-1-4757-4926-7. http:\/\/link.springer.com\/10.1007\/978-1-4757-4926-7."},{"key":"10_CR58","doi-asserted-by":"publisher","unstructured":"S\u00e1nchez-Clemente A, Entrena L, Garc\u00eda-Valderas M, L\u00f3pez-Ongil C. Logic masking for set mitigation using approximate logic circuits. In: 2012 IEEE 18th international on-line testing symposium (IOLTS). 2012. pp. 176\u2013181. https:\/\/doi.org\/10.1109\/IOLTS.2012.6313868.","DOI":"10.1109\/IOLTS.2012.6313868"},{"issue":"4","key":"10_CR59","doi-asserted-by":"publisher","first-page":"1871","DOI":"10.1109\/TR.2016.2604918","volume":"65","author":"A Sanchez-Clemente","year":"2016","unstructured":"Sanchez-Clemente AJ, Entrena L, Hrbacek R, Sekanina L. Error mitigation using approximate logic circuits: A comparison of probabilistic and evolutionary approaches. IEEE Trans Reliab. 2016;65(4):1871\u201383. https:\/\/doi.org\/10.1109\/TR.2016.2604918.","journal-title":"IEEE Trans Reliab"},{"key":"10_CR60","doi-asserted-by":"publisher","unstructured":"Santoro M. New methodologies for eliminating no trouble found, no fault found and other non repeatable failures in depot settings. In: 2008 IEEE AUTOTESTCON. 2008. pp. 336\u201340. https:\/\/doi.org\/10.1109\/AUTEST.2008.4662636. ISSN: 1558-4550.","DOI":"10.1109\/AUTEST.2008.4662636"},{"key":"10_CR61","doi-asserted-by":"crossref","unstructured":"Segura J, Hawkins CF. CMOS electronics: how it works, how it fails. New York: IEEE Press\/Wiley-Interscience; 2004. OCLC: ocm53192483.","DOI":"10.1002\/0471728527"},{"key":"10_CR62","doi-asserted-by":"crossref","unstructured":"Shafique M, Ahmad W, Hafiz R, Henkel J. A low latency generic accuracy configurable adder. In: 2015 52nd ACM\/EDAC\/IEEE design automation conference (DAC). 2015. pp. 1\u20136. https:\/\/doi.org\/10.1145\/2744769.2744778.","DOI":"10.1145\/2744769.2744778"},{"key":"10_CR63","unstructured":"Shivakumar P. Techniques to improve the hard and soft error reliability of distributed architectures. Thesis. 2007. https:\/\/repositories.lib.utexas.edu\/handle\/2152\/3304."},{"issue":"6","key":"10_CR64","doi-asserted-by":"publisher","first-page":"3417","DOI":"10.1109\/TNS.2006.884352","volume":"53","author":"B Sierawski","year":"2006","unstructured":"Sierawski BD, Bhuva BL, Massengill LW. Reducing soft error rate in logic circuits through approximate logic functions. IEEE Trans Nuclear Sci. 2006;53(6):3417\u201321. https:\/\/doi.org\/10.1109\/TNS.2006.884352.","journal-title":"IEEE Trans Nuclear Sci"},{"key":"10_CR65","doi-asserted-by":"crossref","unstructured":"Sosnowski J. Transient fault tolerance in digital systems. IEEE Micro. 1994;14(1):24\u201335. https:\/\/doi.org\/10.1109\/40.259897. http:\/\/ieeexplore.ieee.org\/document\/259897\/.","DOI":"10.1109\/40.259897"},{"key":"10_CR66","doi-asserted-by":"publisher","unstructured":"Srinivasan J, Adve S, Bose P, Rivers J. The case for lifetime reliability-aware microprocessors. In: Proceedings. 31st Annual international symposium on computer architecture. 2004. pp. 276\u2013287. https:\/\/doi.org\/10.1109\/ISCA.2004.1310781.","DOI":"10.1109\/ISCA.2004.1310781"},{"key":"10_CR67","doi-asserted-by":"publisher","unstructured":"Srinivasan J, Adve S, Bose P, Rivers J. The impact of technology scaling on lifetime reliability. In: International conference on dependable systems and networks. 2004. pp. 177\u2013186. https:\/\/doi.org\/10.1109\/DSN.2004.1311888.","DOI":"10.1109\/DSN.2004.1311888"},{"key":"10_CR68","doi-asserted-by":"publisher","unstructured":"Subramanian V, Somani AK. Conjoined pipeline: Enhancing hardware reliability and performance through organized pipeline redundancy. In: 2008 14th IEEE Pacific Rim international symposium on dependable computing. 2008. pp. 9\u201316. https:\/\/doi.org\/10.1109\/PRDC.2008.54.","DOI":"10.1109\/PRDC.2008.54"},{"key":"10_CR69","unstructured":"Traiola M. Test techniques for approximate digital circuits. PhD thesis, Universit\u00e9 Montpellier. 2019. https:\/\/tel.archives-ouvertes.fr\/tel-02485781."},{"key":"10_CR70","doi-asserted-by":"publisher","unstructured":"Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Investigation of mean-error metrics for testing approximate integrated circuits. In: 2018 IEEE international symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFT). 2018. pp. 1\u20136. https:\/\/doi.org\/10.1109\/DFT.2018.8602939.","DOI":"10.1109\/DFT.2018.8602939"},{"key":"10_CR71","doi-asserted-by":"publisher","unstructured":"Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. On the comparison of different ATPG approaches for approximate integrated circuits. In: IEEE 21st international symposium on design and diagnostics of electronic circuits systems. 2018. pp. 85\u201390. https:\/\/doi.org\/10.1109\/DDECS.2018.00022.","DOI":"10.1109\/DDECS.2018.00022"},{"key":"10_CR72","doi-asserted-by":"publisher","unstructured":"Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Testing approximate digital circuits: Challenges and opportunities. In: 2018 IEEE 19th Latin-American test symposium (LATS). 2018. pp. 1\u20136. https:\/\/doi.org\/10.1109\/LATW.2018.8349681.","DOI":"10.1109\/LATW.2018.8349681"},{"key":"10_CR73","doi-asserted-by":"publisher","unstructured":"Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. A test pattern generation technique for approximate circuits based on an ILP-formulated pattern selection procedure. IEEE Trans Nanotechnol. 2019. p. 1. https:\/\/doi.org\/10.1109\/TNANO.2019.2923040.","DOI":"10.1109\/TNANO.2019.2923040"},{"key":"10_CR74","doi-asserted-by":"crossref","unstructured":"Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Maximizing yield for approximate integrated circuits. In: 2020 design, automation test in Europe conference exhibition (DATE). 2020.","DOI":"10.23919\/DATE48585.2020.9116341"},{"issue":"12","key":"10_CR75","doi-asserted-by":"publisher","first-page":"2178","DOI":"10.1109\/JPROC.2020.2999613","volume":"108","author":"M Traiola","year":"2020","unstructured":"Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. A survey of testing techniques for approximate integrated circuits. Proc IEEE. 2020;108(12):2178\u201394. https:\/\/doi.org\/10.1109\/JPROC.2020.2999613.","journal-title":"Proc IEEE"},{"key":"10_CR76","doi-asserted-by":"publisher","unstructured":"Tran D, Virazel A, Bosio A, Dilillo L, Girard P, Pravossoudovitch S, Wunderlich HJ. A hybrid fault tolerant architecture for robustness improvement of digital circuits. In: 2011 Asian test symposium. 2011. pp. 136\u2013141. https:\/\/doi.org\/10.1109\/ATS.2011.89. ISSN: 2377-5386.","DOI":"10.1109\/ATS.2011.89"},{"key":"10_CR77","unstructured":"Wali I. Circuit and system fault tolerance techniques. PhD thesis, Universit\u00e9 Montpellier. 2016. https:\/\/tel.archives-ouvertes.fr\/tel-01807927."},{"key":"10_CR78","doi-asserted-by":"crossref","unstructured":"Wali I, Deveautour B, Virazel A, Bosio A, Girard P, Sonza Reorda M. A low-cost reliability vs. cost trade-off methodology to selectively harden logic circuits. J Electron Test. 2017;33(1):25\u201336. https:\/\/doi.org\/10.1007\/s10836-017-5640-6. https:\/\/doi.org\/10.1007\/s10836-017-5640-6.","DOI":"10.1007\/s10836-017-5640-6"},{"key":"10_CR79","doi-asserted-by":"publisher","unstructured":"Wali I, Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Towards approximation during test of integrated circuits. In: 2017 IEEE 20th international symposium on design and diagnostics of electronic circuits systems (DDECS). 2017. pp. 28\u201333. https:\/\/doi.org\/10.1109\/DDECS.2017.7934574.","DOI":"10.1109\/DDECS.2017.7934574"},{"key":"10_CR80","doi-asserted-by":"publisher","unstructured":"Wali I, Virazel A, Bosio A, Dilillo L, Girard P. An effective hybrid fault-tolerant architecture for pipelined cores. In: 2015 20th IEEE European test symposium (ETS). 2015. pp. 1\u20136. https:\/\/doi.org\/10.1109\/ETS.2015.7138733.","DOI":"10.1109\/ETS.2015.7138733"},{"key":"10_CR81","unstructured":"Weide-Zaage K, Chrzanowska-Jeske M. Semiconductor devices in harsh conditions. https:\/\/www.routledge.com\/Semiconductor-Devices-in-Harsh-Conditions\/Weide-Zaage-Chrzanowska-Jeske\/p\/book\/9780367656362."},{"key":"10_CR82","doi-asserted-by":"crossref","unstructured":"Wirnshofer M. Variation-aware adaptive voltage scaling for digital CMOS circuits. Springer series in advanced microelectronics. Springer Netherlands; 2013. https:\/\/doi.org\/10.1007\/978-94-007-6196-4. https:\/\/www.springer.com\/gp\/book\/9789400761957.","DOI":"10.1007\/978-94-007-6196-4"},{"key":"10_CR83","unstructured":"Yang S. Logic synthesis and optimization benchmarks user guide version 3.0; 1991. https:\/\/doi.org\/10.1.1.49.591."},{"issue":"6","key":"10_CR84","doi-asserted-by":"publisher","first-page":"2852","DOI":"10.1109\/TNS.2012.2223715","volume":"59","author":"J Yao","year":"2012","unstructured":"Yao J, Okada S, Masuda M, Kobayashi K, Nakashima Y. DARA: A low-cost reliable architecture based on unhardened devices and its case study of radiation stress test. IEEE Trans Nuclear Sci. 2012;59(6):2852\u20138. https:\/\/doi.org\/10.1109\/TNS.2012.2223715.","journal-title":"IEEE Trans Nuclear Sci"},{"issue":"2","key":"10_CR85","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1109\/MDAT.2016.2630270","volume":"34","author":"A Yazdanbakhsh","year":"2017","unstructured":"Yazdanbakhsh A, Mahajan D, Esmaeilzadeh H, Lotfi-Kamran P. AxBench: A multiplatform benchmark suite for approximate computing. IEEE Des Test. 2017;34(2):60\u20138. https:\/\/doi.org\/10.1109\/MDAT.2016.2630270.","journal-title":"IEEE Des Test"},{"key":"10_CR86","doi-asserted-by":"publisher","unstructured":"Ye R, Wang T, Yuan F, Kumar R, Xu Q. On reconfiguration-oriented approximate adder design and its application. In: 2013 IEEE\/ACM international conference on computer-aided design (ICCAD). 2013. pp. 48\u201354. https:\/\/doi.org\/10.1109\/ICCAD.2013.6691096.","DOI":"10.1109\/ICCAD.2013.6691096"},{"issue":"1","key":"10_CR87","doi-asserted-by":"publisher","first-page":"155","DOI":"10.1109\/TCAD.2005.853696","volume":"25","author":"Q Zhou","year":"2006","unstructured":"Zhou Q, Mohanram K. Gate sizing to radiation harden combinational logic. IEEE Trans Comput Aided Des Integr Circ Syst. 2006;25(1):155\u201366. https:\/\/doi.org\/10.1109\/TCAD.2005.853696.","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"10_CR88","unstructured":"Zhu N, Goh WL, Yeo KS. An enhanced low-power high-speed adder for error-tolerant application. In: Proceedings of the 2009 12th international symposium on integrated circuits. 2009. pp. 69\u201372."},{"key":"10_CR89","doi-asserted-by":"publisher","unstructured":"Zoellin CG, Wunderlich HJ, Polian I, Becker B. Selective hardening in early design steps. In: 2008 13th European test symposium. 2008. pp. 185\u2013190. https:\/\/doi.org\/10.1109\/ETS.2008.30. ISSN: 1558-1780.","DOI":"10.1109\/ETS.2008.30"}],"container-title":["Approximate Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-98347-5_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,22]],"date-time":"2022-08-22T14:14:34Z","timestamp":1661177674000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-030-98347-5_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783030983468","9783030983475"],"references-count":89,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-98347-5_10","relation":{},"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"18 March 2022","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}