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The original design is transformed into a \u201clocked\u201d design such that the circuit reveals its correct functionality only when it is \u201cunlocked\u201d with a <jats:italic>secret<\/jats:italic> sequence of bits\u2014the <jats:italic>key<\/jats:italic> bit-string. However, strong attacks, especially the <jats:italic>SAT attack<\/jats:italic> that uses a SAT solver to recover the key bit-string, have been profoundly effective at breaking the locked circuit and recovering the circuit functionality.<\/jats:p><jats:p>We lift logic locking to <jats:italic>Higher Order Logic Locking (HOLL)<\/jats:italic> by hiding a higher-order <jats:italic>relation<\/jats:italic>, instead of a key of independent values, challenging the attacker to discover this <jats:italic>key relation<\/jats:italic> to recreate the circuit functionality. Our technique uses <jats:italic>program synthesis<\/jats:italic> to construct the locked design and synthesize a corresponding <jats:italic>key relation<\/jats:italic>. HOLL has low overhead and existing attacks for logic locking do not apply as the entity to be recovered is no more a value. To evaluate our proposal, we propose a new attack (<jats:italic>SynthAttack<\/jats:italic>) that uses an inductive synthesis algorithm guided by an operational circuit as an input-output oracle to recover the hidden functionality. SynthAttack is inspired by the SAT attack, and similar to the SAT attack, it is <jats:italic>verifiably correct<\/jats:italic>, i.e., if the correct functionality is revealed, a verification check guarantees the same. Our empirical analysis shows that SynthAttack can break HOLL for small circuits and small key relations, but it is ineffective for real-life designs.<\/jats:p>","DOI":"10.1007\/978-3-030-99524-9_1","type":"book-chapter","created":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T06:14:55Z","timestamp":1648534495000},"page":"3-24","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":16,"title":["HOLL: Program Synthesis for Higher Order Logic Locking"],"prefix":"10.1007","author":[{"given":"Gourav","family":"Takhar","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7989-5617","authenticated-orcid":false,"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9315-1788","authenticated-orcid":false,"given":"Christian","family":"Pilato","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3394-023X","authenticated-orcid":false,"given":"Subhajit","family":"Roy","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2022,3,30]]},"reference":[{"key":"1_CR1","unstructured":"ISCAS\u201985 benchmarks. https:\/\/filebox.ece.vt.edu\/~mhsiao\/iscas85.html, accessed: 2021-01-10"},{"key":"1_CR2","unstructured":"Where is the eFPGA market and ecosystem headed? https:\/\/semiengineering.com\/where-is-the-efpga-market-and-ecosystem-headed\/, accessed: 2021-05-28"},{"key":"1_CR3","doi-asserted-by":"publisher","unstructured":"Alur, R., Bod\u00edk, R., Dallal, E., Fisman, D., Garg, P., Juniwal, G., Kress-Gazit, H., Madhusudan, P., Martin, M.M.K., Raghothaman, M., Saha, S., Seshia, S.A., Singh, R., Solar-Lezama, A., Torlak, E., Udupa, A.: Syntax-guided synthesis. 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