{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T17:56:17Z","timestamp":1742925377331,"version":"3.40.3"},"publisher-location":"Cham","reference-count":32,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783031073113"},{"type":"electronic","value":"9783031073120"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-031-07312-0_12","type":"book-chapter","created":{"date-parts":[[2022,5,28]],"date-time":"2022-05-28T23:03:31Z","timestamp":1653779011000},"page":"233-255","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["MAPredict: Static Analysis Driven Memory Access Prediction Framework for\u00a0Modern CPUs"],"prefix":"10.1007","author":[{"given":"Mohammad Alaul Haque","family":"Monil","sequence":"first","affiliation":[]},{"given":"Seyong","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jeffrey S.","family":"Vetter","sequence":"additional","affiliation":[]},{"given":"Allen D.","family":"Malony","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,5,29]]},"reference":[{"issue":"11","key":"12_CR1","doi-asserted-by":"publisher","first-page":"1985","DOI":"10.1109\/JPROC.2018.2851190","volume":"106","author":"W Jalby","year":"2018","unstructured":"Jalby, W., Kuck, D., Malony, A., Masella, M., Mazouz, A., Popov, M.: The long and winding road toward efficient high-performance computing. Proc. IEEE 106(11), 1985\u20132003 (2018)","journal-title":"Proc. IEEE"},{"key":"12_CR2","unstructured":"Monil, M.A.H., Belviranli, M., Lee, S., Vetter, J., Malony, A. In: International Conference on Parallel Architectures and Compilation Techniques (PACT), (2020)"},{"issue":"4","key":"12_CR3","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1145\/1498765.1498785","volume":"52","author":"S Williams","year":"2009","unstructured":"Williams, S., Waterman, A., Patterson, D.: Roofline: an insightful visual performance model for multicore architectures. Commun. ACM 52(4), 65\u201376 (2009)","journal-title":"Commun. ACM"},{"key":"12_CR4","doi-asserted-by":"crossref","unstructured":"Lee, S., Meredith, J., Vetter, J.: Compass: a framework for automated performance modeling and prediction. In: 29th International Conference on Supercomputing (ICS15), pp. 405\u2013414 (2015)","DOI":"10.1145\/2751205.2751220"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Peng, I., Vetter, J., Moore, S., Lee, S.: Tuyere: Enabling scalable memory workloads for system exploration. In: International Symposium on High-Performance Parallel and Distributed Computing, pp. 180\u2013191 (2018)","DOI":"10.1145\/3208040.3208057"},{"key":"12_CR6","doi-asserted-by":"publisher","first-page":"222","DOI":"10.1016\/j.jpdc.2017.11.005","volume":"120","author":"M Umar","year":"2018","unstructured":"Umar, M., Moore, S.V., Meredith, J.S., Vetter, J.S., Cameron, K.W.: Aspen-based performance and energy modeling frameworks. J. Parallel Distrib. Compu. 120, 222\u2013236 (2018)","journal-title":"J. Parallel Distrib. Compu."},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Spafford, K.L., Vetter, J.S.: Aspen: a domain specific language for performance modeling. In: SC12: International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1\u201311, Salt Lake City (2012)","DOI":"10.1109\/SC.2012.20"},{"key":"12_CR8","unstructured":"Top 500 supercomputers published at sc20. https:\/\/www.top500.org\/"},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"Alappat, C., Hofmann, J., Hager, G., Fehske, H., Bishop, A., Wellein, G.: Understanding HPC benchmark performance on Intel Broadwell and Cascade Lake processors. arXiv preprint arXiv:2002.03344 (2020)","DOI":"10.2172\/1771077"},{"key":"12_CR10","doi-asserted-by":"crossref","unstructured":"Monil, M.A.H., Lee, S., Vetter, J.S., Malony, A.D.: Comparing LLC-memory traffic between CPU and GPU architectures. In: 2021 IEEE\/ACM Redefining Scalability for Diversely Heterogeneous Architectures Workshop (RSDHA), pp. 8\u201316 (2021)","DOI":"10.1109\/RSDHA54838.2021.00007"},{"issue":"2","key":"12_CR11","doi-asserted-by":"publisher","first-page":"287","DOI":"10.1177\/1094342006064482","volume":"20","author":"S Shende","year":"2006","unstructured":"Shende, S., Malony, A.: The TAU parallel performance system. Int. J. High Perform. Comput. Appl 20(2), 287\u2013311 (2006)","journal-title":"Int. J. High Perform. Comput. Appl"},{"key":"12_CR12","doi-asserted-by":"publisher","unstructured":"Terpstra, D., Jagode, H., You, H., Dongarra, J.: Collecting performance data with PAPI-C. In: Muller, M., Resch, M., Schulz, A., Nagel, W. (eds.) Tools for High Performance Computing 2009, pp. 157\u2013173. Springer, Berlin (2010). https:\/\/doi.org\/10.1007\/978-3-642-11261-4_11","DOI":"10.1007\/978-3-642-11261-4_11"},{"key":"12_CR13","doi-asserted-by":"crossref","unstructured":"Lee, S., Vetter, J.S.: OpenARC: open accelerator research compiler for directive-based, efficient heterogeneous computing. In: ACM Symposium on High-Performance Parallel and Distributed Computing (HPDC), Vancouver, ACM (2014)","DOI":"10.1145\/2600212.2600704"},{"key":"12_CR14","unstructured":"McCalpin, J.D.: Stream benchmarks (2002)"},{"key":"12_CR15","unstructured":"Tramm, J., Siegel, A., Islam, T., Schulz,M.: XSBench-the development and verification of a performance abstraction for Monte Carlo reactor analysis. In: Conference: PHYSOR 2014 - The Role of Reactor Physics toward a Sustainable Future (PHYSOR) (2014)"},{"key":"12_CR16","doi-asserted-by":"crossref","unstructured":"Karlin, I.: Lulesh programming model and performance ports overview. Technical report, Lawrence Livermore National Lab. (LLNL), CA, USA (2012)","DOI":"10.2172\/1059462"},{"key":"12_CR17","doi-asserted-by":"crossref","unstructured":"Yu, L., Li, D., Mittal, S., Vetter, J.S.: Quantitatively modeling application resiliency with the data vulnerability factor. In: ACM\/IEEE International Conference for High Performance Computing, Networking, Storage, and Analysis (SC) (2014)","DOI":"10.1109\/SC.2014.62"},{"issue":"1","key":"12_CR18","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1109\/LCA.2015.2414456","volume":"15","author":"Y Kim","year":"2015","unstructured":"Kim, Y., Yang, W., Mutlu, O.: Ramulator: a fast and extensible DRAM simulator. IEEE Comput. Archit. Lett. 15(1), 45\u201349 (2015)","journal-title":"IEEE Comput. Archit. Lett."},{"issue":"1","key":"12_CR19","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/L-CA.2011.4","volume":"10","author":"P Rosenfeld","year":"2011","unstructured":"Rosenfeld, P., Cooper-Balis, E., Jacob, B.: DRAMSim2: a cycle accurate memory system simulator. IEEE Comput. Archit. Lett. 10(1), 16\u201319 (2011)","journal-title":"IEEE Comput. Archit. Lett."},{"key":"12_CR20","doi-asserted-by":"crossref","unstructured":"Allen, T., Ge, R.: Characterizing power and performance of GPU memory access. In: Internatopnal Workshop on Energy Efficient Supercomputing (E2SC), pp. 46\u201353 (2016)","DOI":"10.1109\/E2SC.2016.012"},{"key":"12_CR21","doi-asserted-by":"crossref","unstructured":"Dave, C., Bae, H., Min, S., Lee, S., Eigenmann, R., Midkiff, S.: Cetus: a source-to-source compiler infrastructure for multicores. Computer 42, 36\u201342 (2009)","DOI":"10.1109\/MC.2009.385"},{"key":"12_CR22","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"90","DOI":"10.1007\/978-3-030-17872-7_6","volume-title":"Programming and Performance Visualization Tools","author":"MG Lopez","year":"2019","unstructured":"Lopez, M.G., Hernandez, O., Budiardja, R.D., Wells, J.C.: CAASCADE: a system for static analysis of HPC software application portfolios. In: Bhatele, A., Boehme, D., Levine, J.A., Malony, A.D., Schulz, M. (eds.) ESPT\/VPA 2017-2018. LNCS, vol. 11027, pp. 90\u2013104. Springer, Cham (2019). https:\/\/doi.org\/10.1007\/978-3-030-17872-7_6"},{"key":"12_CR23","doi-asserted-by":"crossref","unstructured":"Hill, M., Reddi, V.J.: Gables: a roofline model for mobile SoCs. In: International Symposium on High Performance Computer Architecture (HPCA), pp. 317\u2013330 (2019)","DOI":"10.1109\/HPCA.2019.00047"},{"key":"12_CR24","doi-asserted-by":"crossref","unstructured":"Monil, M.A.H., Lee, S., Vetter, J., Malony, A.: Understanding the impact of memory access patterns in Intel processors. In: MCHPC 2020: Workshop on Memory Centric High Performance Computing. IEEE (2020)","DOI":"10.1109\/MCHPC51950.2020.00012"},{"key":"12_CR25","doi-asserted-by":"crossref","unstructured":"Marques, D.: Performance analysis with cache-aware roofline model in Intel advisor. In: International Conference on High Performance Computing & Simulation, pp. 898\u2013907 (2017)","DOI":"10.1109\/HPCS.2017.150"},{"key":"12_CR26","doi-asserted-by":"crossref","unstructured":"Hammond, S., Vaughan, C., Hughes, C.: Evaluating the Intel Skylake Xeon processor for HPC workloads. In: International Conference on High Performance Computing & Simulation (HPCS18), pp. 342\u2013349 (2018)","DOI":"10.1109\/HPCS.2018.00064"},{"key":"12_CR27","doi-asserted-by":"crossref","unstructured":"Molka, D., Hackenberg, D., Sch\u00f6ne, R.: Main memory and cache performance of Intel Sandy Bridge and AMD Bulldozer. In: Proceedings of the Workshop on Memory Systems Performance and Correctness, pp. 1\u201310 (2014)","DOI":"10.1145\/2618128.2618129"},{"key":"12_CR28","doi-asserted-by":"crossref","unstructured":"Treibig, J., Hager, G., Wellein, G.: LIKWID: a lightweight performance-oriented tool suite for x86 multicore environments. In: 2010 39th International Conference on Parallel Processing Workshops, pp. 207\u2013216. IEEE (2010)","DOI":"10.1109\/ICPPW.2010.38"},{"key":"12_CR29","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"210","DOI":"10.1007\/978-3-319-30695-7_16","volume-title":"Architecture of Computing Systems \u2013 ARCS 2016","author":"J Hofmann","year":"2016","unstructured":"Hofmann, J., Fey, D., Eitzinger, J., Hager, G., Wellein, G.: Analysis of Intel\u2019s Haswell microarchitecture using the ECM model and microbenchmarks. In: Hannig, F., Cardoso, J.M.P., Pionteck, T., Fey, D., Schr\u00f6der-Preikschat, W., Teich, J. (eds.) ARCS 2016. LNCS, vol. 9637, pp. 210\u2013222. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-30695-7_16"},{"key":"12_CR30","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"294","DOI":"10.1007\/978-3-319-58667-0_16","volume-title":"High Performance Computing","author":"J Hofmann","year":"2017","unstructured":"Hofmann, J., Hager, G., Wellein, G., Fey, D.: An analysis of core- and chip-level architectural features in four generations of intel server processors. In: Kunkel, J.M., Yokota, R., Balaji, P., Keyes, D. (eds.) ISC High Performance 2017. LNCS, vol. 10266, pp. 294\u2013314. Springer, Cham (2017). https:\/\/doi.org\/10.1007\/978-3-319-58667-0_16"},{"key":"12_CR31","doi-asserted-by":"crossref","unstructured":"Saini, S., Hood, R., Chang, J., Baron, J.: Performance evaluation of an Intel Haswell-and Ivy Bridge-based supercomputer using scientific and engineering applications. In: 2016 IEEE 18th International Conference on High Performance Computing and Communications (HPCC), pp. 1196\u20131203. IEEE (2016)","DOI":"10.1109\/HPCC-SmartCity-DSS.2016.0167"},{"key":"12_CR32","doi-asserted-by":"crossref","unstructured":"Saini, S., Hood, R.: Performance evaluation of Intel Broadwell nodes based supercomputer using computational fluid dynamics and climate applications. In: 2017 IEEE 19th International Conference on High Performance Computing and Communications Workshops (HPCCWS), pp. 58\u201365. IEEE (2017)","DOI":"10.1109\/HPCCWS.2017.00015"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-07312-0_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,26]],"date-time":"2024-09-26T01:34:51Z","timestamp":1727314491000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-07312-0_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783031073113","9783031073120"],"references-count":32,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-07312-0_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"29 May 2022","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ISC High Performance","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on High Performance Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Hamburg","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2022","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"29 May 2022","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2 June 2022","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"37","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"supercomputing2022","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Linklings","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"53","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"18","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"34% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"5","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"For the workshops a 27 papers have been accepted for publication out of a total of 43 submissions.","order":10,"name":"additional_info_on_review_process","label":"Additional Info on Review Process","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}