{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T23:45:01Z","timestamp":1743032701334,"version":"3.40.3"},"publisher-location":"Cham","reference-count":18,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783031161582"},{"type":"electronic","value":"9783031161599"}],"license":[{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023]]},"DOI":"10.1007\/978-3-031-16159-9_22","type":"book-chapter","created":{"date-parts":[[2022,8,31]],"date-time":"2022-08-31T11:02:48Z","timestamp":1661943768000},"page":"266-277","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Verification and\u00a0Benchmarking in\u00a0MPA Coprocessor Design Process"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3952-5731","authenticated-orcid":false,"given":"Tomasz P.","family":"Stefa\u0144ski","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3319-5900","authenticated-orcid":false,"given":"Kamil","family":"Rudnicki","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8714-280X","authenticated-orcid":false,"given":"Wojciech","family":"\u017bebrowski","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,9,1]]},"reference":[{"key":"22_CR1","unstructured":"Aldec Inc.: Riviera-PRO Manual (2017). www.aldec.com. Accessed 08 Aug 2019"},{"issue":"2","key":"22_CR2","doi-asserted-by":"publisher","first-page":"299","DOI":"10.1145\/103516.103519","volume":"38","author":"RE Bryant","year":"1991","unstructured":"Bryant, R.E.: A methodology for hardware verification based on logic simulation. J. ACM 38(2), 299\u2013328 (1991). https:\/\/doi.org\/10.1145\/103516.103519","journal-title":"J. ACM"},{"key":"22_CR3","unstructured":"Granlund, T.: GMP Development Team: The GNU multiple precision arithmetic library (Edition 6.1.2) (2016). www.gmplib.org. Accessed 08 Aug 2019"},{"issue":"2","key":"22_CR4","doi-asserted-by":"publisher","first-page":"470","DOI":"10.1016\/j.net.2015.12.008","volume":"48","author":"J Kim","year":"2016","unstructured":"Kim, J., Kim, E.S., Yoo, J., Lee, Y.J., Choi, J.G.: An integrated software testing framework for FPGA-based controllers in nuclear power plants. Nucl. Eng. Technol. 48(2), 470\u2013481 (2016). https:\/\/doi.org\/10.1016\/j.net.2015.12.008","journal-title":"Nucl. Eng. Technol."},{"key":"22_CR5","doi-asserted-by":"publisher","unstructured":"Lissel, R., Gerlach, J.: Introducing new verification methods into a company\u2019s design flow: an industrial user\u2019s point of view. In: 2007 Design, Automation and Test in Europe Conference and Exhibition, pp. 1\u20136 (2007). https:\/\/doi.org\/10.1109\/DATE.2007.364675","DOI":"10.1109\/DATE.2007.364675"},{"key":"22_CR6","doi-asserted-by":"publisher","unstructured":"Rudnicki, K., Stefanski, T.P.: IP core of coprocessor for multiple-precision-arithmetic computations. In: 2018 25th International Conference Mixed Design of Integrated Circuits and System (MIXDES), pp. 416\u2013419 (2018). https:\/\/doi.org\/10.23919\/MIXDES.2018.8436868","DOI":"10.23919\/MIXDES.2018.8436868"},{"key":"22_CR7","doi-asserted-by":"publisher","unstructured":"Rudnicki, K., Stefa\u0144ski, T.P.: Implementation of addition and subtraction operations in multiple precision arithmetic. In: 2019 MIXDES - 26th International Conference Mixed Design of Integrated Circuits and Systems, pp. 231\u2013235 (2019). https:\/\/doi.org\/10.23919\/MIXDES.2019.8787156","DOI":"10.23919\/MIXDES.2019.8787156"},{"key":"22_CR8","unstructured":"Rudnicki, K., Stefa\u0144ski, T.P., \u017bebrowski, W.: Integer-MPA-coprocessor (2020). https:\/\/github.com\/stafan26\/integer-MPA-coprocessor"},{"key":"22_CR9","doi-asserted-by":"publisher","unstructured":"Rudnicki, K., Stefa\u0144ski, T.P., \u017bebrowski, W.: Open-source coprocessor for integer multiple precision arithmetic. Electronics 9(7), 1141 (2020). https:\/\/doi.org\/10.3390\/electronics9071141","DOI":"10.3390\/electronics9071141"},{"key":"22_CR10","doi-asserted-by":"crossref","unstructured":"Stefa\u0144ski, T.: Applications of the discrete green\u2019s function in the finite-difference time-domain method. Prog. Electromagn. Res.-PIER 139, 479\u2013498 (2013). https:\/\/www.jpier.org\/PIER\/pier.php?paper=13032906","DOI":"10.2528\/PIER13032906"},{"key":"22_CR11","doi-asserted-by":"publisher","first-page":"1002","DOI":"10.1109\/LAWP.2015.2388955","volume":"14","author":"TP Stefa\u0144ski","year":"2015","unstructured":"Stefa\u0144ski, T.P.: A new expression for the 3-D dyadic FDTD-compatible green\u2019s function based on multidimensional z-transform. IEEE Antennas Wirel. Propag. Lett. 14, 1002\u20131005 (2015). https:\/\/doi.org\/10.1109\/LAWP.2015.2388955","journal-title":"IEEE Antennas Wirel. Propag. Lett."},{"key":"22_CR12","doi-asserted-by":"publisher","unstructured":"Stefa\u0144ski, T.P., Rudnicki, K., \u017bebrowski, W.: Implementation of coprocessor for integer multiple precision arithmetic on Zynq Ultrascale+ MPSoC. In: 2021 28th International Conference on Mixed Design of Integrated Circuits and System, pp. 280\u2013285 (2021). https:\/\/doi.org\/10.23919\/MIXDES52406.2021.9497554","DOI":"10.23919\/MIXDES52406.2021.9497554"},{"key":"22_CR13","doi-asserted-by":"crossref","unstructured":"Stefa\u0144ski, T.: Discrete green\u2019s function approach to disjoint domain simulations in 3D FDTD method. Electron. Lett. 49, 597\u2013598 (2013). https:\/\/digital-library.theiet.org\/content\/journals\/10.1049\/el.2012.4462","DOI":"10.1049\/el.2012.4462"},{"key":"22_CR14","doi-asserted-by":"publisher","unstructured":"Vemuri, R., Kalyanaraman, R.: Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3(2), 201\u2013214 (1995). https:\/\/doi.org\/10.1109\/92.386221","DOI":"10.1109\/92.386221"},{"key":"22_CR15","unstructured":"Xilinx Inc.: Integrated Logic Analyzer v6.2 - LogiCORE IP Product Guide, PG172 (2016). www.xilinx.com. Accessed 08 Aug 2019"},{"key":"22_CR16","unstructured":"Xilinx Inc.: Vivado Design Suite User Guide - Getting Started, UG910 (v2018.3) (2018). www.xilinx.com. Accessed 08 Aug 2019"},{"key":"22_CR17","unstructured":"Xilinx Inc.: Xilinx Quick Emulator User Guide, UG1169 (v2020.1) (2020). www.xilinx.com. Accessed 24 Mar 2022"},{"key":"22_CR18","doi-asserted-by":"publisher","unstructured":"Zheng, D., Wang, Y., Xueyi, Z.: The methods of FPGA software verification. In: 2011 IEEE International Conference on Computer Science and Automation Engineering, vol. 3, pp. 86\u201389 (2011). https:\/\/doi.org\/10.1109\/CSAE.2011.5952639","DOI":"10.1109\/CSAE.2011.5952639"}],"container-title":["Lecture Notes in Networks and Systems","Intelligent and Safe Computer Systems in Control and Diagnostics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-16159-9_22","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,26]],"date-time":"2022-09-26T10:06:19Z","timestamp":1664186779000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-16159-9_22"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,9,1]]},"ISBN":["9783031161582","9783031161599"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-16159-9_22","relation":{},"ISSN":["2367-3370","2367-3389"],"issn-type":[{"type":"print","value":"2367-3370"},{"type":"electronic","value":"2367-3389"}],"subject":[],"published":{"date-parts":[[2022,9,1]]},"assertion":[{"value":"1 September 2022","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DPS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Diagnostics of Processes and Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Chmielno","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Poland","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2022","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"5 September 2022","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"7 September 2022","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"15","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"dps2022","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/dps2022.konsulting.gda.pl\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}