{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T23:01:22Z","timestamp":1742943682125,"version":"3.40.3"},"publisher-location":"Cham","reference-count":28,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031168178"},{"type":"electronic","value":"9783031168185"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-031-16818-5_5","type":"book-chapter","created":{"date-parts":[[2022,9,28]],"date-time":"2022-09-28T07:07:51Z","timestamp":1664348871000},"page":"93-111","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["A DfT Strategy for\u00a0Detecting Emerging Faults in\u00a0RRAMs"],"prefix":"10.1007","author":[{"given":"Thiago Santos","family":"Copetti","sequence":"first","affiliation":[]},{"given":"Tobias","family":"Gemmeke","sequence":"additional","affiliation":[]},{"given":"Leticia Maria Bolzani","family":"Poehls","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2022,9,22]]},"reference":[{"key":"5_CR1","unstructured":"Moore, G.E.: Cramming more components onto integrated circuits with unit cost. Electronics 38(8), 114 (1965). https:\/\/newsroom.intel.com\/wp-content\/uploads\/sites\/11\/2018\/05\/moores-law-electronics.pdf"},{"issue":"5","key":"5_CR2","doi-asserted-by":"publisher","first-page":"257","DOI":"10.1109\/JSSC.1974.1050511","volume":"9","author":"R Dennard","year":"1974","unstructured":"Dennard, R., Gaensslen, F., Yu, W.-N., Rideout, L., Bassous, E., Le Blanc, A.: Design of ion-implanted small MOSFET. S dimensions with very. IEEE J. Solid State Circ. 9(5), 257\u2013268 (1974)","journal-title":"IEEE J. Solid State Circ."},{"key":"5_CR3","doi-asserted-by":"crossref","unstructured":"Hamdioui, S., et al.: Memristor for computing: myth or reality? In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., pp. 722\u2013731 (2017)","DOI":"10.23919\/DATE.2017.7927083"},{"issue":"6","key":"5_CR4","doi-asserted-by":"publisher","first-page":"1911","DOI":"10.1109\/JPROC.2012.2190812","volume":"100","author":"P Mazumder","year":"2012","unstructured":"Mazumder, P., Kang, S.M., Waser, R.: Memristors: devices, models, and applications. Proc. IEEE 100(6), 1911\u20131919 (2012)","journal-title":"Proc. IEEE"},{"key":"5_CR5","doi-asserted-by":"crossref","unstructured":"Chaudhuri, A., Chakrabarty, K.: Analysis of process variations, defects, and design-induced coupling in memristors. In: 2018 IEEE International Test Conference (ITC), pp. 1\u201310 (2018)","DOI":"10.1109\/TEST.2018.8624819"},{"issue":"4","key":"5_CR6","doi-asserted-by":"publisher","first-page":"427","DOI":"10.1007\/s10836-021-05968-8","volume":"37","author":"LMB Poehls","year":"2021","unstructured":"Poehls, L.M.B., et al.: Review of manufacturing process defects and their effects on memristive devices. J. Electron. Test. 37(4), 427\u2013437 (2021). https:\/\/doi.org\/10.1007\/s10836-021-05968-8","journal-title":"J. Electron. Test."},{"issue":"1","key":"5_CR7","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1109\/TC.2013.206","volume":"64","author":"S Hamdioui","year":"2015","unstructured":"Hamdioui, S., Taouil, M., Haron, N.Z.: Testing open defects in memristor-based memories. IEEE Trans. Comput. 64(1), 247\u2013259 (2015)","journal-title":"IEEE Trans. Comput."},{"key":"5_CR8","doi-asserted-by":"crossref","unstructured":"Haron, N.Z., Hamdioui, S.: DFT schemes for resistive open defects in RRAMs. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 799\u2013804. IEEE (2012)","DOI":"10.1109\/DATE.2012.6176603"},{"issue":"1","key":"5_CR9","doi-asserted-by":"publisher","first-page":"247","DOI":"10.1109\/TC.2013.206","volume":"64","author":"S Hamdioui","year":"2013","unstructured":"Hamdioui, S., Taouil, M., Haron, N.Z.: Testing open defects in memristor-based memories. IEEE Trans. Comput. 64(1), 247\u2013259 (2013)","journal-title":"IEEE Trans. Comput."},{"key":"5_CR10","doi-asserted-by":"crossref","unstructured":"Fieback, M., et al.: Device-aware test: a new test approach towards DPPB level. In: Proceedings - International Test Conference, vol. 2019-Novem (2019)","DOI":"10.1109\/ITC44170.2019.9000134"},{"key":"5_CR11","doi-asserted-by":"crossref","unstructured":"Fieback, M., Taouil, M., Hamdioui, S.: Testing resistive memories: where are we and what is missing? In: 2018 IEEE International Test Conference (ITC), pp. 1\u20139 (2018)","DOI":"10.1109\/TEST.2018.8624895"},{"issue":"3","key":"5_CR12","doi-asserted-by":"publisher","first-page":"413","DOI":"10.1109\/TNANO.2013.2253329","volume":"12","author":"S Kannan","year":"2013","unstructured":"Kannan, S., Rajendran, J., Karri, R., Sinanoglu, O.: Sneak-path testing of crossbar-based nonvolatile random access memories. IEEE Trans. Nanotechnol. 12(3), 413\u2013426 (2013)","journal-title":"IEEE Trans. Nanotechnol."},{"key":"5_CR13","doi-asserted-by":"crossref","unstructured":"Copetti, T.S., Gemmeke, T., Poehls, L.B.: Validating a DFT strategy\u2019s detection capability regarding emerging faults in RRAMs. In: 2021 IFIP\/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1\u20136 (2021)","DOI":"10.1109\/VLSI-SoC53125.2021.9606993"},{"key":"5_CR14","unstructured":"Jart vcm v1b. http:\/\/www.emrl.de\/JART.html. Accessed 11 Apr 2021"},{"issue":"5","key":"5_CR15","doi-asserted-by":"publisher","first-page":"507","DOI":"10.1109\/TCT.1971.1083337","volume":"CT\u201318","author":"L Chua","year":"1971","unstructured":"Chua, L.: Memristor - the missing current element. IEEE Trans. Circ. Theory CT\u201318(5), 507\u2013519 (1971)","journal-title":"IEEE Trans. Circ. Theory"},{"issue":"3","key":"5_CR16","doi-asserted-by":"publisher","first-page":"493","DOI":"10.1109\/TETC.2017.2691263","volume":"7","author":"EI Vatajelu","year":"2017","unstructured":"Vatajelu, E.I., Prinetto, P., Taouil, M., Hamdioui, S.: Challenges and solutions in emerging memory testing. IEEE Trans. Emerg. Top. Comput. 7(3), 493\u2013506 (2017)","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"key":"5_CR17","doi-asserted-by":"crossref","unstructured":"Waser, R.: Electrochemical and thermochemical memories. In: Technical Digest - International Electron Devices Meeting, IEDM (2008)","DOI":"10.1109\/IEDM.2008.4796675"},{"key":"5_CR18","doi-asserted-by":"crossref","unstructured":"Yu, J., Du Nguyen, H.A., Xie, L., Taouil, M., Hamdioui, S.: Memristive devices for computation-in-memory. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1646\u20131651. IEEE (2018)","DOI":"10.23919\/DATE.2018.8342278"},{"issue":"4","key":"5_CR19","doi-asserted-by":"publisher","first-page":"1121","DOI":"10.1007\/s10825-017-1101-9","volume":"16","author":"D Ielmini","year":"2017","unstructured":"Ielmini, D., Milo, V.: Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications. J. Comput. Electron. 16(4), 1121\u20131143 (2017). https:\/\/doi.org\/10.1007\/s10825-017-1101-9","journal-title":"J. Comput. Electron."},{"issue":"25\u201326","key":"5_CR20","doi-asserted-by":"publisher","first-page":"2632","DOI":"10.1002\/adma.200900375","volume":"21","author":"R Waser","year":"2009","unstructured":"Waser, R., Dittmann, R., Staikov, C., Szot, K.: Redox-based resistive switching memories nanoionic mechanisms, prospects, and challenges. Adv. Mater. 21(25\u201326), 2632\u20132663 (2009)","journal-title":"Adv. Mater."},{"issue":"8","key":"5_CR21","doi-asserted-by":"publisher","first-page":"3229","DOI":"10.1109\/TED.2018.2849872","volume":"65","author":"A Hardtdegen","year":"2018","unstructured":"Hardtdegen, A., La Torre, C., Cuppers, F., Menzel, S., Waser, R., Hoffmann-Eifert, S.: Improved switching stability and the effect of an internal series resistor in HfO2\/TiOx Bilayer ReRAM cells. IEEE Trans. Electron Devices 65(8), 3229\u20133236 (2018)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"6","key":"5_CR22","doi-asserted-by":"publisher","first-page":"1271","DOI":"10.1109\/TVLSI.2021.3071940","volume":"29","author":"GC Medeiros","year":"2021","unstructured":"Medeiros, G.C., et al.: Hard-to-detect fault analysis in finfet srams. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 29(6), 1271\u20131284 (2021)","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"5_CR23","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"39","DOI":"10.1007\/BFb0018367","volume-title":"Knowledge Based Computer Systems","author":"S Arvindam","year":"1990","unstructured":"Arvindam, S., Kumar, V., Nageshwara Rao, V., Singh, V.: Automatic test pattern generation on multiprocessors: a summary of results. In: Ramani, S., Chandrasekar, R., Anjaneyulu, K.S.R. (eds.) KBCS 1989. LNCS, vol. 444, pp. 39\u201351. Springer, Heidelberg (1990). https:\/\/doi.org\/10.1007\/BFb0018367"},{"key":"5_CR24","doi-asserted-by":"crossref","unstructured":"Haron, N. Z., Hamdioui, S.: On defect oriented testing for hybrid CMOS\/memristor memory. In: 2011 Asian Test Symposium, pp. 353\u2013358. IEEE (2011)","DOI":"10.1109\/ATS.2011.66"},{"issue":"1","key":"5_CR25","doi-asserted-by":"publisher","first-page":"180","DOI":"10.1109\/TC.2014.12","volume":"64","author":"C-Y Chen","year":"2014","unstructured":"Chen, C.-Y., et al.: Rram defect modeling and failure analysis based on march test and a novel squeeze-search scheme. IEEE Trans. Comput. 64(1), 180\u2013190 (2014)","journal-title":"IEEE Trans. Comput."},{"key":"5_CR26","doi-asserted-by":"crossref","unstructured":"Chen, Y.X., Li, J.F.: Fault modeling and testing of 1T1R memristor memories. In: 2015 IEEE 33rd VLSI Test Symposium (VTS), pp. 1\u20136. IEEE (2015)","DOI":"10.1109\/VTS.2015.7116247"},{"key":"5_CR27","doi-asserted-by":"crossref","unstructured":"Kannan, S., Rajendran, J., Karri, R., Sinanoglu, O.: Sneak-path testing of memristor-based memories. In: 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, pp. 386\u2013391. IEEE (2013)","DOI":"10.1109\/VLSID.2013.219"},{"key":"5_CR28","unstructured":"Rabaey, J.M., Chandrakasan, A.P., Nikoli\u0107, B.: Digital integrated circuits: a design perspective, vol. 7. Pearson education Upper Saddle River, NJ (2003)"}],"container-title":["IFIP Advances in Information and Communication Technology","VLSI-SoC: Technology Advancement on SoC Design"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-16818-5_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,9,28]],"date-time":"2022-09-28T07:13:30Z","timestamp":1664349210000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-16818-5_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783031168178","9783031168185"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-16818-5_5","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"22 September 2022","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"VLSI-SoC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"IFIP\/IEEE International Conference on Very Large Scale Integration - System on a Chip","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2021","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4 October 2021","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"8 October 2021","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"29","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"vlsi-soc2021","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/vlsisoc.github.io\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}