{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T05:13:03Z","timestamp":1743052383044,"version":"3.40.3"},"publisher-location":"Cham","reference-count":24,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031217494"},{"type":"electronic","value":"9783031217500"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-031-21750-0_10","type":"book-chapter","created":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T01:22:43Z","timestamp":1672536163000},"page":"115-126","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Design and\u00a0FPGA Realization of\u00a0an\u00a0Energy Efficient Artificial Neural Modular Exponentiation Architecture"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4826-1640","authenticated-orcid":false,"given":"C.","family":"Pakkiraiah","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R. V. S.","family":"Satyanarayana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,1,1]]},"reference":[{"key":"10_CR1","doi-asserted-by":"publisher","first-page":"800","DOI":"10.1016\/j.procs.2020.04.087","volume":"171","author":"V Reddy","year":"2020","unstructured":"Reddy, V., Singh, S., Desalphine, V., Selvakumar, D.: A low latency montgomery modular exponentiation. Procedia Comput. Sci. 171, 800\u2013809 (2020)","journal-title":"Procedia Comput. Sci."},{"key":"10_CR2","doi-asserted-by":"crossref","unstructured":"Daly, A., Marnane, W.: Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. In: Proceedings of the 2002 ACM\/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, pp. 40\u201349 (2002)","DOI":"10.1145\/503048.503055"},{"issue":"8","key":"10_CR3","doi-asserted-by":"publisher","first-page":"892","DOI":"10.1109\/12.295851","volume":"43","author":"P Kornerup","year":"1994","unstructured":"Kornerup, P.: A systolic, linear-array multiplier for a class of right-shift algorithms. IEEE Trans. Comput. 43(8), 892\u2013898 (1994)","journal-title":"IEEE Trans. Comput."},{"issue":"8","key":"10_CR4","doi-asserted-by":"publisher","first-page":"962","DOI":"10.1109\/12.156539","volume":"41","author":"MA Hasan","year":"1992","unstructured":"Hasan, M.A., Wang, M., Bhargava, V.K.: Modular construction of low complexity parallel multipliers for a class of finite fields GF($$2^{m}$$). IEEE Trans. Comput. 41(8), 962\u2013971 (1992)","journal-title":"IEEE Trans. Comput."},{"key":"10_CR5","doi-asserted-by":"crossref","unstructured":"Xiao, H., Yu, S., Cheng, B., Liu, G.: FPGA-based high-throughput montgomery modular multipliers for RSA cryptosystems. IEICE Electron. Express 19, 20220101 (2022)","DOI":"10.1587\/elex.19.20220101"},{"key":"10_CR6","doi-asserted-by":"crossref","unstructured":"Venkatesh, K., Pratibha, K., Annadurai, S., Kuppusamy, L.: Reconfigurable architecture to speed-up modular exponentiation. In: 2019 International Carnahan Conference on Security Technology (ICCST), pp. 1\u20136. IEEE (2019)","DOI":"10.1109\/CCST.2019.8888401"},{"key":"10_CR7","doi-asserted-by":"crossref","unstructured":"Li, S., et al.: Research in fast modular exponentiation algorithm based on FPGA. In: 2019 11th International Conference on Measuring Technology and Mechatronics Automation (ICMTMA), pp. 79\u201382. IEEE (2019)","DOI":"10.1109\/ICMTMA.2019.00024"},{"issue":"06","key":"10_CR8","doi-asserted-by":"publisher","first-page":"540","DOI":"10.1109\/TC.1982.1676036","volume":"31","author":"FJ Taylor","year":"1982","unstructured":"Taylor, F.J.: A VLSI residue arithmetic multiplier. IEEE Trans. Comput. 31(06), 540\u2013546 (1982)","journal-title":"IEEE Trans. Comput."},{"key":"10_CR9","doi-asserted-by":"crossref","unstructured":"Shieh, M.D., Chen, J.H., Wu, H.H., Lin, W.C.: A new modular exponentiation architecture for efficient design of RSA cryptosystem. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(9), 1151\u20131161 (2008)","DOI":"10.1109\/TVLSI.2008.2000524"},{"key":"10_CR10","unstructured":"Raghuraman, S., Nazhandali, L.: Does gate count matter? Hardware efficiency of logic-minimization techniques for cryptographic primitives"},{"key":"10_CR11","doi-asserted-by":"crossref","unstructured":"Das, S., Dasgupta, P., Fiser, P., Ghosh, S., Das, D. K.: A rule-based approach for minimizing power dissipation of digital circuits. In: 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp. 1\u20136. IEEE (2016)","DOI":"10.1109\/DDECS.2016.7482470"},{"issue":"1","key":"10_CR12","doi-asserted-by":"publisher","first-page":"861","DOI":"10.12785\/ijcds\/110171","volume":"11","author":"C Pakkiraiah","year":"2022","unstructured":"Pakkiraiah, C., Satyanarayana, D.R.: An innovative design of low power binary adder based on switching activity. Int. J. Comput. Digit. Syst. 11(1), 861\u2013871 (2022)","journal-title":"Int. J. Comput. Digit. Syst."},{"key":"10_CR13","unstructured":"HOI, H.T.: Design and analysis of full adders using reversible logic (2021)"},{"issue":"03","key":"10_CR14","first-page":"117","volume":"8","author":"R Sabbaghi","year":"2019","unstructured":"Sabbaghi, R., Dehbozorgi, L., Akbari-Hasanjani, R.: New full adders using multi-layer perceptron network. Int. J. Smart Electr. Eng. 8(03), 117\u2013122 (2019)","journal-title":"Int. J. Smart Electr. Eng."},{"issue":"12","key":"10_CR15","first-page":"1","volume":"184","author":"C Pakkiraiah","year":"2022","unstructured":"Pakkiraiah, C., Satyanarayana, R.V.S.: Design of low power artificial hybrid adder using neural network classifiers to minimize energy delay product for arithmetic application. Int. J. Comput. Appl. 184(12), 1\u20138 (2022)","journal-title":"Int. J. Comput. Appl."},{"key":"10_CR16","unstructured":"Pakkiraiah, C., Satyanarayana, R.V.S.: Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits. IUP J. Electr. Electron. Eng. 15(2), 42\u201358 (2022)"},{"key":"10_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"185","DOI":"10.1007\/3-540-44709-1_17","volume-title":"Cryptographic Hardware and Embedded Systems \u2014 CHES 2001","author":"AF Tenca","year":"2001","unstructured":"Tenca, A.F., Todorov, G., Ko\u00e7, \u00c7.K.: High-radix design of a scalable modular multiplier. In: Ko\u00e7, \u00c7.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 185\u2013201. Springer, Heidelberg (2001). https:\/\/doi.org\/10.1007\/3-540-44709-1_17"},{"key":"10_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"523","DOI":"10.1007\/3-540-45539-6_37","volume-title":"Advances in Cryptology \u2014 EUROCRYPT 2000","author":"S Kawamura","year":"2000","unstructured":"Kawamura, S., Koike, M., Sano, F., Shimbo, A.: Cox-rower architecture for fast parallel montgomery multiplication. In: Preneel, B. (ed.) EUROCRYPT 2000. LNCS, vol. 1807, pp. 523\u2013538. Springer, Heidelberg (2000). https:\/\/doi.org\/10.1007\/3-540-45539-6_37"},{"issue":"7","key":"10_CR19","doi-asserted-by":"publisher","first-page":"759","DOI":"10.1109\/12.936241","volume":"50","author":"T Blum","year":"2001","unstructured":"Blum, T., Paar, C.: High-radix montgomery modular exponentiation on reconfigurable hardware. IEEE Trans. Comput. 50(7), 759\u2013764 (2001)","journal-title":"IEEE Trans. Comput."},{"issue":"1","key":"10_CR20","doi-asserted-by":"publisher","first-page":"84","DOI":"10.1109\/12.980018","volume":"51","author":"AA Hiasat","year":"2002","unstructured":"Hiasat, A.A.: High-speed and reduced-area modular adder structures for RNS. IEEE Trans. Comput. 51(1), 84\u201389 (2002)","journal-title":"IEEE Trans. Comput."},{"issue":"7","key":"10_CR21","doi-asserted-by":"publisher","first-page":"908","DOI":"10.1109\/82.700944","volume":"45","author":"CC Yang","year":"1998","unstructured":"Yang, C.C., Chang, T.S., Jen, C.W.: A new RSA cryptosystem hardware design based on montgomery\u2019s algorithm. IEEE Trans. Circuits Syst. II: Analog Digit. Sign. Process. 45(7), 908\u2013913 (1998)","journal-title":"IEEE Trans. Circuits Syst. II: Analog Digit. Sign. Process."},{"key":"10_CR22","unstructured":"Shand, M., Vuillemin, J.: Fast implementations of RSA cryptography. In: Proceedings of IEEE 11th Symposium on Computer Arithmetic, pp. 252\u2013259. IEEE (1993)"},{"key":"10_CR23","doi-asserted-by":"crossref","unstructured":"Nadjia, A., Mohamed, A.: FPGA Implementation of the M-ary Modular Exponentiation. In: 2013 8th IEEE Design and Test Symposium, pp. 1\u20132. IEEE (2013)","DOI":"10.1109\/IDT.2013.6727140"},{"key":"10_CR24","doi-asserted-by":"crossref","unstructured":"Pakkiraiah, C., Satyanarayana, R.V.S.: FPGA realization of low power multi-layer perceptron full adder to minimize EDP of modular multiplier. Int. J. Electron. Eng. Appl. 10(2), 01-12 (2022)","DOI":"10.30696\/IJEEA.X.II.2022.01-12"}],"container-title":["Communications in Computer and Information Science","Computing, Communication and Learning"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-21750-0_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T01:33:55Z","timestamp":1672536835000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-21750-0_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783031217494","9783031217500"],"references-count":24,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-21750-0_10","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"1 January 2023","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"CoCoLe","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Computing, Communication and Learning","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Warangal","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2022","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"27 October 2022","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"29 October 2022","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"cocole2022","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/ic-cocole.in\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"117","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"25","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"1","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"21% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}