{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:16:25Z","timestamp":1759331785111,"version":"3.40.3"},"publisher-location":"Cham","reference-count":18,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783031218668"},{"type":"electronic","value":"9783031218675"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-031-21867-5_2","type":"book-chapter","created":{"date-parts":[[2022,12,13]],"date-time":"2022-12-13T11:04:07Z","timestamp":1670929447000},"page":"17-32","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Dual-IS: Instruction Set Modality for\u00a0Efficient Instruction Level Parallelism"],"prefix":"10.1007","author":[{"given":"Kari","family":"Hepola","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joonas","family":"Multanen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pekka","family":"J\u00e4\u00e4skel\u00e4inen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2022,12,14]]},"reference":[{"key":"2_CR1","unstructured":"Albartus, N., Nasenberg, C., Stolz, F., Fyrbiak, M., Paar, C., Tessier, R.: On the design and misuse of microcoded (embedded) processors-a cautionary note. In: 30th USENIX Security Symposium (USENIX Security 21) (2021)"},{"issue":"2","key":"2_CR2","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1109\/MM.2015.12","volume":"35","author":"D Boggs","year":"2015","unstructured":"Boggs, D., Brown, G., Tuck, N., Venkatraman, K.: Denver: Nvidia\u2019s first 64-bit ARM processor. IEEE Micro 35(2), 46\u201355 (2015)","journal-title":"IEEE Micro"},{"issue":"12\u201313","key":"2_CR3","doi-asserted-by":"publisher","first-page":"949","DOI":"10.1016\/S1383-7621(98)00046-0","volume":"45","author":"H Corporaal","year":"1999","unstructured":"Corporaal, H.: TTAs: missing the ILP complexity wall. J. Syst. Architect. 45(12\u201313), 949\u2013973 (1999)","journal-title":"J. Syst. Architect."},{"key":"2_CR4","doi-asserted-by":"publisher","first-page":"113454","DOI":"10.1109\/ACCESS.2021.3104150","volume":"9","author":"M Crepaldi","year":"2021","unstructured":"Crepaldi, M., Merello, A., Di Salvo, M.: A multi-one instruction set computer for microcontroller applications. IEEE Access 9, 113454\u2013113474 (2021)","journal-title":"IEEE Access"},{"key":"2_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1007\/978-3-540-70550-5_4","volume-title":"Embedded Computer Systems: Architectures, Modeling, and Simulation","author":"V Guzma","year":"2008","unstructured":"Guzma, V., J\u00e4\u00e4skel\u00e4inen, P., Kellom\u00e4ki, P., Takala, J.: Impact of software bypassing on instruction level parallelism and register file traffic. In: Berekovi\u0107, M., Dimopoulos, N., Wong, S. (eds.) SAMOS 2008. LNCS, vol. 5114, pp. 23\u201332. Springer, Heidelberg (2008). https:\/\/doi.org\/10.1007\/978-3-540-70550-5_4"},{"key":"2_CR6","doi-asserted-by":"crossref","unstructured":"Hara, Y., Tomiyama, H., Honda, S., Takada, H., Ishii, K.: CHStone: a benchmark program suite for practical C-based high-level synthesis. In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS) (2008)","DOI":"10.2197\/ipsjjip.17.242"},{"key":"2_CR7","doi-asserted-by":"crossref","unstructured":"Hepola, K., Multanen, J., J\u00e4skel\u00e4inen, P.: OpenASIP 2.0: co-design toolset for RISC-V application-specific instruction-set processors. In: IEEE 33rd International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2022)","DOI":"10.1109\/ASAP54787.2022.00034"},{"key":"2_CR8","doi-asserted-by":"crossref","unstructured":"Hoogerbrugge, J., Corporaal, H.: Register file port requirements of transport triggered architectures. In: Proceedings of the 27th Annual International Symposium on Microarchitecture. MICRO 27, Association for Computing Machinery (1994)","DOI":"10.1145\/192724.192751"},{"key":"2_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"435","DOI":"10.1007\/3-540-57877-3_29","volume-title":"Compiler Construction","author":"J Hoogerbrugge","year":"1994","unstructured":"Hoogerbrugge, J., Corporaal, H.: Transport-triggering vs. operation-triggering. In: Fritzson, P.A. (ed.) CC 1994. LNCS, vol. 786, pp. 435\u2013449. Springer, Heidelberg (1994). https:\/\/doi.org\/10.1007\/3-540-57877-3_29"},{"key":"2_CR10","unstructured":"Horowitz, M., Indermaur, T., Gonzalez, R.: Low-power digital design. In: Proceedings of 1994 IEEE Symposium on Low Power Electronics (1994)"},{"key":"2_CR11","doi-asserted-by":"crossref","unstructured":"Hou, Y., et al.: FuMicro: a fused microarchitecture design integrating in-order superscalar and VLIW. VLSI Design (2016)","DOI":"10.1155\/2016\/8787919"},{"issue":"1","key":"2_CR12","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1007\/s11265-014-0924-x","volume":"80","author":"P J\u00e4\u00e4skel\u00e4inen","year":"2014","unstructured":"J\u00e4\u00e4skel\u00e4inen, P., Kultala, H., Viitanen, T., Takala, J.: Code density and energy efficiency of exposed datapath architectures. J. Sig. Process. Syst. 80(1), 49\u201364 (2014). https:\/\/doi.org\/10.1007\/s11265-014-0924-x","journal-title":"J. Sig. Process. Syst."},{"key":"2_CR13","doi-asserted-by":"crossref","unstructured":"Karaki, H., Akkary, H., Shahidzadeh, S.: X86-ARM binary hardware interpreter. In: 2011 18th IEEE International Conference on Electronics, Circuits, and Systems (2011)","DOI":"10.1109\/ICECS.2011.6122235"},{"key":"2_CR14","unstructured":"Klaiber, A.: The technology behind Crusoe processors. Transmeta Techn. Brief (2000)"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"Klemmer, L., Gro\u00dfe, D.: An exploration platform for microcoded RISC-V cores leveraging the one instruction set computer principle. In: 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2022)","DOI":"10.1109\/ISVLSI54635.2022.00020"},{"key":"2_CR16","doi-asserted-by":"crossref","unstructured":"Li, S., Chen, K., Ahn, J.H., Brockman, J.B., Jouppi, N.P.: CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. In: 2011 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) (2011)","DOI":"10.1109\/ICCAD.2011.6105405"},{"key":"2_CR17","doi-asserted-by":"crossref","unstructured":"Lin, T.J., et al.: A unified processor architecture for RISC & VLIW DSP. In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI. Association for Computing Machinery (2005)","DOI":"10.1145\/1057661.1057675"},{"key":"2_CR18","doi-asserted-by":"crossref","unstructured":"Taylor, M.B.: Is dark silicon useful? harnessing the four horsemen of the coming dark silicon apocalypse. In: DAC Design Automation Conference 2012 (2012)","DOI":"10.1145\/2228360.2228567"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-21867-5_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,13]],"date-time":"2022-12-13T11:04:17Z","timestamp":1670929457000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-21867-5_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783031218668","9783031218675"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-21867-5_2","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"14 December 2022","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARCS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Architecture of Computing Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Heilbronn","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2022","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"13 September 2022","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"15 September 2022","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"35","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arcs2022","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/arcs-conference.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"35","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"18","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"51% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3,87","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}