{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T00:46:37Z","timestamp":1742949997917,"version":"3.40.3"},"publisher-location":"Cham","reference-count":27,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783031218668"},{"type":"electronic","value":"9783031218675"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-031-21867-5_9","type":"book-chapter","created":{"date-parts":[[2022,12,13]],"date-time":"2022-12-13T11:04:07Z","timestamp":1670929447000},"page":"132-147","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Using Look Up\u00a0Table Content as\u00a0Signatures to\u00a0Identify IP Cores in\u00a0Modern FPGAs"],"prefix":"10.1007","author":[{"given":"Ali","family":"Asghar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amanda Katherine","family":"Robillard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ilya","family":"Tuzov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Becher","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Ziener","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2022,12,14]]},"reference":[{"key":"9_CR1","unstructured":"Global semiconductor sales increase 6.5% to \\$439 billion in 2020 (2021). https:\/\/www.semiconductors.org\/global-semiconductor-sales-increase-6-5-to-439-billion-in-2020\/"},{"key":"9_CR2","unstructured":"Protecting the FPGA design from common threats. Altera (2009)"},{"key":"#cr-split#-9_CR3.1","unstructured":"Bozzoli, L., Sterpone, L.: Comet: a configuration memory tool to analyze, visualize and manipulate FPGAs bitstream. In: ARCS Workshop 2018"},{"key":"#cr-split#-9_CR3.2","unstructured":"31th International Conference on Architecture of Computing Systems. VDE (2018)"},{"key":"9_CR4","unstructured":"Brayton, R., et al.: Berkeley logic synthesis and verification group, ABC: a system for sequential synthesis and verification"},{"key":"9_CR5","doi-asserted-by":"crossref","unstructured":"Chen, M., Liu, P.: A deep learning-based FPGA function block detection method with bitstream to image transformation, vol. 9. IEEE (2021)","DOI":"10.1109\/ACCESS.2021.3096664"},{"key":"9_CR6","unstructured":"Cobham Gaisler AB: GRLIB IP core user manual, 2022.1 (2022)"},{"key":"9_CR7","doi-asserted-by":"crossref","unstructured":"Courtland, R.: Transistors will stop shrinking in 2021, Moore\u2019s law roadmap - predicts the last itrs report forecasts an end to traditional 2D scaling. IEEE Spectrum (2016)","DOI":"10.1109\/MSPEC.2016.7551335"},{"key":"9_CR8","unstructured":"Dauman, A.: An open IP encryption flow permits industry-wide interoperability. In: White Paper. Synopsys, Inc. (2006)"},{"key":"9_CR9","unstructured":"Ender, M., Moradi, A., Paar, C.: The unpatchable silicon: a full break of the bitstream encryption of xilinx 7-series $$\\{$$FPGAs$$\\}$$. In: 29th USENIX Security Symposium (USENIX Security 20) (2020)"},{"issue":"4","key":"9_CR10","doi-asserted-by":"publisher","first-page":"15","DOI":"10.1109\/54.632877","volume":"14","author":"RK Gupta","year":"1997","unstructured":"Gupta, R.K., Zorian, Y.: Introducing core-based system design. IEEE Des. Test Comput. 14(4), 15\u201325 (1997)","journal-title":"IEEE Des. Test Comput."},{"key":"9_CR11","doi-asserted-by":"crossref","unstructured":"Huang, Z., Wang, L., Nasikovskiy, Y., Mishchenko, A.: Fast Boolean matching based on NPN classification. In: 2013 International Conference on Field-Programmable Technology (FPT). IEEE (2013)","DOI":"10.1109\/FPT.2013.6718374"},{"key":"9_CR12","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., et al.: Constraint-based watermarking techniques for design IP protection. vol. 20. IEEE (2001)","DOI":"10.1109\/43.952740"},{"key":"9_CR13","doi-asserted-by":"crossref","unstructured":"Mahmood, S., Rettkowski, J., Shallufa, A., H\u00fcbner, M., G\u00f6hringer, D.: IP core identification in FPGA configuration files using machine learning techniques. In: 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin). IEEE (2019)","DOI":"10.1109\/ICCE-Berlin47944.2019.8966236"},{"key":"9_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"71","DOI":"10.1007\/978-3-319-43283-0_5","volume-title":"Constructive Side-Channel Analysis and Secure Design","author":"A Moradi","year":"2016","unstructured":"Moradi, A., Schneider, T.: Improved side-channel analysis attacks on Xilinx bitstream encryption of 5, 6, and 7 series. In: Standaert, F.-X., Oswald, E. (eds.) COSADE 2016. LNCS, vol. 9689, pp. 71\u201387. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-43283-0_5"},{"key":"9_CR15","unstructured":"Pham, K.D., Horta, E., Koch, D.: BITMAN: a tool and API for FPGA bitstream manipulations. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. IEEE (2017)"},{"key":"9_CR16","doi-asserted-by":"crossref","unstructured":"Schmid, M., Ziener, D., Teich, J.: Netlist-level IP protection by watermarking for LUT-based FPGAs. In: 2008 International Conference on Field-Programmable Technology. IEEE (2008)","DOI":"10.1109\/FPT.2008.4762385"},{"key":"9_CR17","doi-asserted-by":"crossref","unstructured":"Tajik, S., Lohrke, H., Seifert, J.P., Boit, C.: On the power of optical contactless probing: attacking bitstream encryption of FPGAs. In: Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (2017)","DOI":"10.1145\/3133956.3134039"},{"key":"9_CR18","unstructured":"Tuzov, I.: Dependability-driven strategies to improve the design and verification of safety-critical HDL-based embedded systems. Ph.D. thesis, Universitat Polit\u00e8cnica de Val\u00e8ncia (2020)"},{"key":"9_CR19","doi-asserted-by":"crossref","unstructured":"Tuzov, I., de Andr\u00e9s, D., Ruiz, J.C.: DAVOS: EDA toolkit for dependability assessment, verification, optimisation and selection of hardware models. In: 2018 48th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN). IEEE (2018)","DOI":"10.1109\/DSN.2018.00042"},{"key":"9_CR20","unstructured":"Wilkinson, K.: Using encryption to secure a 7 series FPGA bitstream, technical report. Technical report, Xilinx (2015)"},{"key":"9_CR21","unstructured":"Xilinx Inc.: 7 Series FPGAs Configurable Logic Block. UG474 (2017)"},{"key":"9_CR22","unstructured":"Xilinx Inc.: Vivado Design Suite TCL Command Reference Guide UG835 (v2019.2) (2019)"},{"key":"9_CR23","doi-asserted-by":"crossref","unstructured":"Yu, Y., Moraitis, M., Dubrova, E.: Can deep learning break a true random number generator? vol. 68. IEEE (2021)","DOI":"10.1109\/TCSII.2021.3066338"},{"key":"9_CR24","doi-asserted-by":"crossref","unstructured":"Zhou, X., Wang, L., Mishchenko, A.: Fast exact NPN classification by co-designing canonical form and its computation algorithm, vol. 69. IEEE (2020)","DOI":"10.1109\/TC.2020.2971466"},{"key":"9_CR25","doi-asserted-by":"crossref","unstructured":"Ziener, D., A\u00dfmus, S., Teich, J.: Identifying FPGA IP-cores based on lookup table content analysis. In: 2006 International Conference on Field Programmable Logic and Applications. IEEE (2006)","DOI":"10.1109\/FPL.2006.311255"},{"issue":"1","key":"9_CR26","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1007\/s11265-007-0136-8","volume":"51","author":"D Ziener","year":"2008","unstructured":"Ziener, D., Teich, J.: Power signature watermarking of IP cores for FPGAs. J. Sig. Process. Syst. 51(1), 123\u2013136 (2008)","journal-title":"J. Sig. Process. Syst."}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-21867-5_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,13]],"date-time":"2022-12-13T11:05:45Z","timestamp":1670929545000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-21867-5_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783031218668","9783031218675"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-21867-5_9","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"14 December 2022","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ARCS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Architecture of Computing Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Heilbronn","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2022","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"13 September 2022","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"15 September 2022","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"35","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"arcs2022","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/arcs-conference.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"35","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"18","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"51% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3,87","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}