{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,20]],"date-time":"2025-12-20T22:16:19Z","timestamp":1766268979394,"version":"3.40.3"},"publisher-location":"Cham","reference-count":23,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031236051"},{"type":"electronic","value":"9783031236068"}],"license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022]]},"DOI":"10.1007\/978-3-031-23606-8_14","type":"book-chapter","created":{"date-parts":[[2023,1,17]],"date-time":"2023-01-17T11:05:14Z","timestamp":1673953514000},"page":"227-243","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Adrastea: An Efficient FPGA Design Environment for\u00a0Heterogeneous Scientific Computing and\u00a0Machine Learning"],"prefix":"10.1007","author":[{"given":"Aaron R.","family":"Young","sequence":"first","affiliation":[]},{"given":"Narasinga Rao","family":"Miniskar","sequence":"additional","affiliation":[]},{"given":"Frank","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Willem","family":"Blokland","sequence":"additional","affiliation":[]},{"given":"Jeffrey S.","family":"Vetter","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,1,18]]},"reference":[{"key":"14_CR1","doi-asserted-by":"publisher","unstructured":"Cabrera, A.M., Young, A.R., Vetter, J.S.: Design and analysis of cxl performance models for tightly-coupled heterogeneous computing. In: Proceedings of the 1st International Workshop on Extreme Heterogeneity Solutions, ExHET 2022. Association for Computing Machinery, New York (2022). https:\/\/doi.org\/10.1145\/3529336.3530817","DOI":"10.1145\/3529336.3530817"},{"key":"14_CR2","doi-asserted-by":"crossref","unstructured":"Chacko, J., Sahin, C., Nguyen, D., Pfeil, D., Kandasamy, N., Dandekar, K.: FPGA-based latency-insensitive OFDM pipeline for wireless research. In: 2014 IEEE High Performance Extreme Computing Conference (HPEC), pp. 1\u20136. IEEE (2014)","DOI":"10.1109\/HPEC.2014.7040969"},{"key":"14_CR3","doi-asserted-by":"publisher","unstructured":"Cock, D., et al.: Enzian: an open, general, CPU\/FPGA platform for systems software research. In: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2022, pp. 434\u2013451. Association for Computing Machinery, New York (2022). https:\/\/doi.org\/10.1145\/3503222.3507742","DOI":"10.1145\/3503222.3507742"},{"key":"14_CR4","doi-asserted-by":"crossref","unstructured":"Dufour, C., Cense, S., Ould-Bachir, T., Gr\u00e9goire, L.A., B\u00e9langer, J.: General-purpose reconfigurable low-latency electric circuit and motor drive solver on FPGA. In: IECON 2012-38th Annual Conference on IEEE Industrial Electronics Society, pp. 3073\u20133081. IEEE (2012)","DOI":"10.1109\/IECON.2012.6389407"},{"key":"14_CR5","doi-asserted-by":"crossref","unstructured":"Farabet, C., Poulet, C., Han, J.Y., LeCun, Y.: CNP: an FPGA-based processor for convolutional networks. In: 2009 International Conference on Field Programmable Logic and Applications, pp. 32\u201337. IEEE (2009)","DOI":"10.1109\/FPL.2009.5272559"},{"issue":"05","key":"14_CR6","doi-asserted-by":"publisher","first-page":"P05004","DOI":"10.1088\/1748-0221\/7\/05\/P05004","volume":"7","author":"R Giordano","year":"2012","unstructured":"Giordano, R., Aloisio, A.: Protocol-independent, fixed-latency links with FPGA-embedded serdeses. J. Instrum. 7(05), P05004 (2012)","journal-title":"J. Instrum."},{"key":"14_CR7","doi-asserted-by":"publisher","first-page":"610","DOI":"10.1016\/j.nima.2014.03.067","volume":"763","author":"S Henderson","year":"2014","unstructured":"Henderson, S., et al.: The spallation neutron source accelerator system design. Nucl. Instrum. Methods Phys. Res. Sect. A 763, 610\u2013673 (2014)","journal-title":"Nucl. Instrum. Methods Phys. Res. Sect. A"},{"issue":"1","key":"14_CR8","doi-asserted-by":"publisher","first-page":"132","DOI":"10.1080\/17517575.2018.1493145","volume":"13","author":"B Huang","year":"2019","unstructured":"Huang, B., Huan, Y., Xu, L.D., Zheng, L., Zou, Z.: Automated trading systems statistical and machine learning methods and hardware implementation: a survey. Enterp. Inf. Syst. 13(1), 132\u2013144 (2019)","journal-title":"Enterp. Inf. Syst."},{"key":"14_CR9","doi-asserted-by":"publisher","first-page":"178811","DOI":"10.1109\/ACCESS.2019.2958491","volume":"7","author":"MM Islam","year":"2019","unstructured":"Islam, M.M., Hossain, M.S., Hasan, M.K., Shahjalal, M., Jang, Y.M.: FPGA implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field. IEEE Access 7, 178811\u2013178826 (2019)","journal-title":"IEEE Access"},{"issue":"2","key":"14_CR10","doi-asserted-by":"publisher","first-page":"214","DOI":"10.1002\/cta.2295","volume":"45","author":"K Javeed","year":"2017","unstructured":"Javeed, K., Wang, X.: Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF (P). Int. J. Circuit Theory Appl. 45(2), 214\u2013228 (2017)","journal-title":"Int. J. Circuit Theory Appl."},{"key":"14_CR11","doi-asserted-by":"publisher","unstructured":"Kathail, V.: Xilinx vitis unified software platform. In: Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2020, pp. 173\u2013174. Association for Computing Machinery, New York (2020). https:\/\/doi.org\/10.1145\/3373087.3375887","DOI":"10.1145\/3373087.3375887"},{"key":"14_CR12","doi-asserted-by":"publisher","unstructured":"Kim, J., Lee, S., Johnston, B., Vetter, J.S.: IRIS: a portable runtime system exploiting multiple heterogeneous programming systems. In: Proceedings of the 25th IEEE High Performance Extreme Computing Conference, HPEC 2021, pp. 1\u20138 (2021). https:\/\/doi.org\/10.1109\/HPEC49654.2021.9622873","DOI":"10.1109\/HPEC49654.2021.9622873"},{"key":"14_CR13","doi-asserted-by":"crossref","unstructured":"Liu, F., Miniskar, N.R., Chakraborty, D., Vetter, J.S.: Deffe: a data-efficient framework for performance characterization in domain-specific computing. In: Proceedings of the 17th ACM International Conference on Computing Frontiers, pp. 182\u2013191 (2020)","DOI":"10.1145\/3387902.3392633"},{"key":"14_CR14","doi-asserted-by":"crossref","unstructured":"Lockwood, J.W., Gupte, A., Mehta, N., Blott, M., English, T., Vissers, K.: A low-latency library in FPGA hardware for high-frequency trading (HFT). In: 2012 IEEE 20th Annual Symposium on High-Performance Interconnects, pp. 9\u201316. IEEE (2012)","DOI":"10.1109\/HOTI.2012.15"},{"key":"14_CR15","doi-asserted-by":"crossref","unstructured":"Miniskar, N., Young, A., Liu, F., Blokland, W., Cabrera, A., Vetter, J.: Ultra low latency machine learning for scientific edge applications. In: Proceedings of 32nd International Conference on Field Programmable Logic and Applications (FPL 2022). IEEE (2022)","DOI":"10.1109\/FPL57034.2022.00068"},{"key":"14_CR16","doi-asserted-by":"crossref","unstructured":"Morris, G.W., Thomas, D.B., Luk, W.: FPGA accelerated low-latency market data feed processing. In: 2009 17th IEEE Symposium on High Performance Interconnects, pp. 83\u201389. IEEE (2009)","DOI":"10.1109\/HOTI.2009.17"},{"key":"14_CR17","doi-asserted-by":"crossref","unstructured":"Pu\u0161, V., Kekely, L., Ko\u0159enek, J.: Low-latency modular packet header parser for FPGA. In: 2012 ACM\/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), pp. 77\u201378. IEEE (2012)","DOI":"10.1145\/2396556.2396571"},{"issue":"4","key":"14_CR18","doi-asserted-by":"publisher","first-page":"853","DOI":"10.1109\/TII.2015.2431223","volume":"11","author":"JJ Rodr\u00edguez-Andina","year":"2015","unstructured":"Rodr\u00edguez-Andina, J.J., Valdes-Pena, M.D., Moure, M.J.: Advanced features and industrial applications of FPGAs-a review. IEEE Trans. Industr. Inf. 11(4), 853\u2013864 (2015)","journal-title":"IEEE Trans. Industr. Inf."},{"key":"14_CR19","unstructured":"Sarkar, T.: DOEPY design of experiments. https:\/\/doepy.readthedocs.io\/en\/latest\/. Accessed 30 Sept 2020"},{"key":"14_CR20","doi-asserted-by":"crossref","unstructured":"Sidler, D., Alonso, G., Blott, M., Karras, K., Vissers, K., Carley, R.: Scalable 10GBPS TCP\/IP stack architecture for reconfigurable hardware. In: 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 36\u201343. IEEE (2015)","DOI":"10.1109\/FCCM.2015.12"},{"issue":"1","key":"14_CR21","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1038\/ncomms13290","volume":"7","author":"S Somnath","year":"2016","unstructured":"Somnath, S., Belianinov, A., Kalinin, S.V., Jesse, S.: Rapid mapping of polarization switching through complete information acquisition. Nat. Commun. 7(1), 1\u20138 (2016). https:\/\/doi.org\/10.1038\/ncomms13290","journal-title":"Nat. Commun."},{"issue":"4","key":"14_CR22","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3495531","volume":"27","author":"Z Wang","year":"2022","unstructured":"Wang, Z., Schafer, B.C.: Learning from the past: efficient high-level synthesis design space exploration for FPGAs. ACM Trans. Des. Autom. Electron. Syst. 27(4), 1\u201323 (2022). https:\/\/doi.org\/10.1145\/3495531","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"14_CR23","unstructured":"Xilinx: Vitis high-level synthesis user guide (UG1399) (2022). https:\/\/docs.xilinx.com\/r\/en-US\/ug1399-vitis-hls"}],"container-title":["Communications in Computer and Information Science","Accelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-23606-8_14","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,3,21]],"date-time":"2023-03-21T08:17:17Z","timestamp":1679386637000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-23606-8_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022]]},"ISBN":["9783031236051","9783031236068"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-23606-8_14","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2022]]},"assertion":[{"value":"18 January 2023","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SMC","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Smoky Mountains Computational Sciences and Engineering Conference","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Kingsport, TN","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"USA","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2022","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23 August 2022","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"25 August 2022","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"smc2022","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/smc2022.ornl.gov\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easychair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"74","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"24","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"32% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}