{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T05:18:50Z","timestamp":1743052730652,"version":"3.40.3"},"publisher-location":"Cham","reference-count":15,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031264993"},{"type":"electronic","value":"9783031265006"}],"license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023]]},"DOI":"10.1007\/978-3-031-26500-6_8","type":"book-chapter","created":{"date-parts":[[2023,2,16]],"date-time":"2023-02-16T12:02:57Z","timestamp":1676548977000},"page":"91-100","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Towards ASIP Architecture-Driven Algorithm Development"],"prefix":"10.1007","author":[{"given":"Manil Dev","family":"Gomony","sequence":"first","affiliation":[]},{"given":"Mihaela","family":"Jivanescu","sequence":"additional","affiliation":[]},{"given":"Nikolas","family":"Olaziregi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,2,17]]},"reference":[{"key":"8_CR1","unstructured":"Cadence Design Systems Inc.: Tensilica customizable processors (2019). https:\/\/ip.cadence.com\/ipportfolio\/tensilica-ip\/xtensa-customizable"},{"key":"8_CR2","unstructured":"Codasip Ltd.: Codasip Studio (2019). https:\/\/www.codasip.com\/custom-processor\/"},{"key":"8_CR3","doi-asserted-by":"publisher","unstructured":"Eusse, J., Williams, C., Leupers, R.: CoEx: a novel profiling-based algorithm\/architecture co-exploration for ASIP design. In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1\u20138 (2013). https:\/\/doi.org\/10.1109\/ReCoSoC.2013.6581520","DOI":"10.1109\/ReCoSoC.2013.6581520"},{"key":"8_CR4","doi-asserted-by":"publisher","unstructured":"Eusse, J., et al.: Pre-architectural performance estimation for ASIP design based on abstract processor models. In: 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp. 133\u2013140 (2014). https:\/\/doi.org\/10.1109\/SAMOS.2014.6893204","DOI":"10.1109\/SAMOS.2014.6893204"},{"issue":"1","key":"8_CR5","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1155\/ASP\/2006\/46472","volume":"2006","author":"RR Hoare","year":"2006","unstructured":"Hoare, R.R., et al.: Rapid VLIW processor customization for signal processing applications using combinational hardware functions. EURASIP J. Adv. Signal Process. 2006(1), 1\u201323 (2006). https:\/\/doi.org\/10.1155\/ASP\/2006\/46472","journal-title":"EURASIP J. Adv. Signal Process."},{"key":"8_CR6","volume-title":"Customizable Embedded Processors: Design Technologies and Applications","author":"P Ienne","year":"2007","unstructured":"Ienne, P., Leupers, R.: Customizable Embedded Processors: Design Technologies and Applications. Morgan Kaufmann Publishers Inc., San Francisco (2007)"},{"key":"8_CR7","doi-asserted-by":"publisher","unstructured":"Jordans, R., Diken, E., Jozwiak, L., Corporaal, H.: BuildMaster: efficient ASIP architecture exploration through compilation and simulation result caching. In: 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems, pp. 83\u201388 (2014). https:\/\/doi.org\/10.1109\/DDECS.2014.6868768","DOI":"10.1109\/DDECS.2014.6868768"},{"key":"8_CR8","doi-asserted-by":"publisher","unstructured":"Jordans, R., J\u00f3\u017awiak, L., Corporaal, H.: Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. In: 2014 3rd Mediterranean Conference on Embedded Computing (MECO), pp. 32\u201335 (2014). https:\/\/doi.org\/10.1109\/MECO.2014.6862720","DOI":"10.1109\/MECO.2014.6862720"},{"key":"8_CR9","doi-asserted-by":"publisher","unstructured":"Jozwiak, L., et al.: ASAM: automatic architecture synthesis and application mapping. Microprocess. Microsyst. 37(8 PARTC), 1002\u20131019 (2013). https:\/\/doi.org\/10.1016\/j.micpro.2013.08.006","DOI":"10.1016\/j.micpro.2013.08.006"},{"key":"8_CR10","doi-asserted-by":"publisher","unstructured":"Kato, T., et al.: A CDFG generating method from C program for LSI design. In: 2008 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, pp. 936\u2013939 (2008). https:\/\/doi.org\/10.1109\/APCCAS.2008.4746177","DOI":"10.1109\/APCCAS.2008.4746177"},{"issue":"8","key":"8_CR11","doi-asserted-by":"publisher","first-page":"889","DOI":"10.1109\/TCAD.2002.800451","volume":"21","author":"VS Lapinskii","year":"2002","unstructured":"Lapinskii, V.S., Jacome, M.F., De Veciana, G.A.: Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), 889\u2013903 (2002). https:\/\/doi.org\/10.1109\/TCAD.2002.800451","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"8_CR12","doi-asserted-by":"publisher","unstructured":"Meloni, P., Pomata, S., Tuveri, G., Secchi, S., Raffo, L., Lindwer, M.: Enabling fast ASIP design space exploration: an FPGA-based runtime reconfigurable prototyper. VLSI Des. 2012, 11:11 (2012). https:\/\/doi.org\/10.1155\/2012\/580584","DOI":"10.1155\/2012\/580584"},{"key":"8_CR13","doi-asserted-by":"publisher","unstructured":"Pomata, S., et al.: Exploiting binary translation for fast ASIP design space exploration on FPGAs. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 566\u2013569 (2012). https:\/\/doi.org\/10.1109\/DATE.2012.6176533","DOI":"10.1109\/DATE.2012.6176533"},{"key":"8_CR14","unstructured":"Rosien, M., Smit, G., Krol, T.: Generating a CDFG from C\/C++ code, pp. 200\u2013202. STW Technology Foundation (2002). Imported from DIES"},{"key":"8_CR15","unstructured":"Synopsys Inc.: Synopsys IP designer (2019). https:\/\/www.synopsys.com\/dw\/ipdir.php?ds=asip-designer"}],"container-title":["IFIP Advances in Information and Communication Technology","Analysis, Estimations, and Applications of Embedded Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-26500-6_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,2,16]],"date-time":"2023-02-16T12:04:37Z","timestamp":1676549077000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-26500-6_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"ISBN":["9783031264993","9783031265006"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-26500-6_8","relation":{},"ISSN":["1868-4238","1868-422X"],"issn-type":[{"type":"print","value":"1868-4238"},{"type":"electronic","value":"1868-422X"}],"subject":[],"published":{"date-parts":[[2023]]},"assertion":[{"value":"17 February 2023","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"IESS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Embedded Systems Symposium","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Friedrichshafen","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"9 September 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11 September 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"iess2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/iess.org\/IESS2019\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"EasyChair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"32","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"16","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"50% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3-4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}