{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,2]],"date-time":"2026-05-02T15:14:02Z","timestamp":1777734842634,"version":"3.51.4"},"publisher-location":"Cham","reference-count":28,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031321795","type":"print"},{"value":"9783031321801","type":"electronic"}],"license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023]]},"DOI":"10.1007\/978-3-031-32180-1_6","type":"book-chapter","created":{"date-parts":[[2023,5,11]],"date-time":"2023-05-11T12:02:53Z","timestamp":1683806573000},"page":"88-100","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["PHAc: Posit Hardware Accelerator for\u00a0Efficient Arithmetic Logic Operations"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7585-6984","authenticated-orcid":false,"given":"Diksha","family":"Shekhawat","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8720-1582","authenticated-orcid":false,"given":"Jugal","family":"Gandhi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3384-3501","authenticated-orcid":false,"given":"M.","family":"Santosh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9937-7438","authenticated-orcid":false,"given":"Jai Gopal","family":"Pandey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,5,12]]},"reference":[{"key":"6_CR1","unstructured":"IEEE standard for floating-point arithmetic, IEEE Std 754\u20132019 (Revision of IEEE 754\u20132008), pp. 1\u201384 (2019)"},{"key":"6_CR2","unstructured":"van Dam, L.: Enabling high performance posit arithmetic applications using hardware acceleration (2018)"},{"issue":"2","key":"6_CR3","first-page":"71","volume":"4","author":"JL Gustafson","year":"2017","unstructured":"Gustafson, J.L., Yonemoto, I.T.: Beating floating point at its own game: posit arithmetic. Supercomput. Front. Innov. 4(2), 71\u201386 (2017)","journal-title":"Supercomput. Front. Innov."},{"key":"6_CR4","doi-asserted-by":"crossref","unstructured":"Sravya, A.M., Swetha, N., Panigrahy, A.K.: Hardware posit numeration system primarily based on arithmetic operations. In: 2022 3rd International Conference for Emerging Technology (INCET), pp. 1\u20138 (2022)","DOI":"10.1109\/INCET54531.2022.9825011"},{"key":"6_CR5","unstructured":"Gustafson, J.L.: The End of Error: Unum Computing. Chapman and Hall\/CRC, Boca Raton (2017)"},{"key":"6_CR6","doi-asserted-by":"crossref","unstructured":"Buoncristiani, N., Shah, S., Donofrio, D., Shalf, J.: Evaluating the numerical stability of posit arithmetic. In: 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), (New Orleans, LA, USA, USA), pp. 612\u2013621. IEEE, 18\u201322 May 2020","DOI":"10.1109\/IPDPS47924.2020.00069"},{"issue":"3","key":"6_CR7","doi-asserted-by":"publisher","first-page":"1241","DOI":"10.1109\/TETC.2022.3187199","volume":"10","author":"D Mallas\u00e9n","year":"2022","unstructured":"Mallas\u00e9n, D., Murillo, R., Del Barrio, A.A., Botella, G., Pi\u00f1uel, L., Prieto-Matias, M.: PERCIVAL: open-source posit RISC-V core with quire capability. IEEE Trans. Emerg. Top. Comput. 10(3), 1241\u20131252 (2022)","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"key":"6_CR8","doi-asserted-by":"crossref","unstructured":"van Dam, L., Peltenburg, J., Al-Ars, Z., Hofstee, H.P.: An accelerator for posit arithmetic targeting posit level 1 blas routines and pair-hmm. In: Proceedings of the Conference for Next Generation Arithmetic 2019, CoNGA 2019, (New York, NY, USA), Association for Computing Machinery (2019)","DOI":"10.1145\/3316279.3316284"},{"key":"6_CR9","doi-asserted-by":"crossref","unstructured":"Jaiswal, M.K., So, H.K.-H.: Architecture generator for type-3 unum posit adder\/subtractor. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), (Florence, Italy), pp. 1\u20135. IEEE, 27\u201313 May 2018","DOI":"10.1109\/ISCAS.2018.8351142"},{"key":"6_CR10","doi-asserted-by":"crossref","unstructured":"Chaurasiya, R., et al.: Parameterized posit arithmetic hardware generator. In: 2018 IEEE 36th International Conference on Computer Design (ICCD), (Orlando, FL, USA, USA), pp. 334\u2013341. IEEE, 7\u201310 October 2018","DOI":"10.1109\/ICCD.2018.00057"},{"key":"6_CR11","doi-asserted-by":"crossref","unstructured":"Barua, H.B., Mondal, K.C.: Approximate computing: a survey of recent trends-bringing greenness to computing and communication. J. Inst. Eng. (India) Ser. B 100(6), 619\u2013626 (2019)","DOI":"10.1007\/s40031-019-00418-8"},{"key":"6_CR12","doi-asserted-by":"crossref","unstructured":"Mart\u00edn-Hernando, Y., Rodr\u00edguez-Ramos, L.F., Garcia-Talavera, M.R.: Fixed-point vs. floating-point arithmetic comparison for adaptive optics real-time control computation. In: Adaptive Optics Systems, vol. 7015, p. 70152Z (2008). International Society for Optics and Photonics","DOI":"10.1117\/12.787408"},{"key":"6_CR13","doi-asserted-by":"crossref","unstructured":"Sasidharan, A., Nagarajan, P.: VHDL implementation of IEEE 754 floating point unit. In: International Conference on Information Communication and Embedded Systems (ICICES2014), pp. 1\u20135 (2014)","DOI":"10.1109\/ICICES.2014.7033999"},{"key":"6_CR14","doi-asserted-by":"crossref","unstructured":"Shekhawat, D., Jangir, A., Pandey, J.G.: A hardware generator for posit arithmetic and its FPGA prototyping. In: 2021 25th International Symposium on VLSI Design and Test (VDAT), pp. 1\u20136. IEEE (2021)","DOI":"10.1109\/VDAT53777.2021.9601025"},{"key":"6_CR15","doi-asserted-by":"publisher","first-page":"74586","DOI":"10.1109\/ACCESS.2019.2920936","volume":"7","author":"MK Jaiswal","year":"2019","unstructured":"Jaiswal, M.K., So, H.K.-H.: PACoGen: a hardware posit arithmetic core generator. IEEE Access 7, 74586\u201374601 (2019)","journal-title":"IEEE Access"},{"key":"6_CR16","doi-asserted-by":"crossref","unstructured":"Jaiswal, M.K., So, H.K.H.: Universal number posit arithmetic generator on FPGA. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), (Dresden, Germany), pp. 1159\u20131162. IEEE, 19\u201323 March 2018","DOI":"10.23919\/DATE.2018.8342187"},{"issue":"94720\u20131776","key":"6_CR17","first-page":"11","volume":"754","author":"W Kahan","year":"1996","unstructured":"Kahan, W.: IEEE standard 754 for binary floating-point arithmetic. Lect. Notes Status IEEE 754(94720\u20131776), 11 (1996)","journal-title":"Lect. Notes Status IEEE"},{"key":"6_CR18","doi-asserted-by":"crossref","unstructured":"Jaiswal, M.K., So, H.K.-H.: Architecture generator for type-3 Unum posit adder\/subtractor. In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1\u20135 (2018)","DOI":"10.1109\/ISCAS.2018.8351142"},{"key":"6_CR19","doi-asserted-by":"crossref","unstructured":"Gustafson, J.L., Yonemoto, I.T.: Beating floating point at its own game: posit arithmetic. Supercomput. Front. Innov. Int. J. 4, 71\u201386 (2017)","DOI":"10.14529\/jsfi170206"},{"key":"6_CR20","doi-asserted-by":"crossref","unstructured":"Hou, J., Zhu, Y., Du, S., Song, S.: Enhancing accuracy and dynamic range of scientific data analytics by implementing posit arithmetic on FPGA. J. Signal Process. Syst. 91, 1137\u20131148 (2019)","DOI":"10.1007\/s11265-018-1420-5"},{"key":"6_CR21","doi-asserted-by":"crossref","unstructured":"Xiao, F., Liang, F., Wu, B., Liang, J., Cheng, S., Zhang, G.: Posit arithmetic hardware implementations with the minimum cost divider and squareroot. Electronics 9(10), 1622 (2020)","DOI":"10.3390\/electronics9101622"},{"key":"6_CR22","doi-asserted-by":"crossref","unstructured":"Mal\u00edk, P.: High throughput floating-point dividers implemented in FPGA. In: 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp. 291\u2013294 (2015)","DOI":"10.1109\/DDECS.2015.66"},{"key":"6_CR23","doi-asserted-by":"crossref","unstructured":"Mallas\u00e9n, D., Murillo, R., Del Barrio, A.A., Botella, G., Pi\u00f1uel, L., Prieto-Matias, M.: Customizing the CVA6 RISC-V core to integrate posit and quire instructions. In: 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), pp. 01\u201306. IEEE (2022)","DOI":"10.1109\/DCIS55711.2022.9970026"},{"issue":"4","key":"6_CR24","doi-asserted-by":"publisher","first-page":"1898","DOI":"10.1109\/TETC.2021.3120538","volume":"10","author":"M Cococcioni","year":"2022","unstructured":"Cococcioni, M., Rossi, F., Ruffaldi, E., Saponara, S.: A lightweight posit processing unit for RISC-V processors in deep neural network applications. IEEE Trans. Emerg. Top. Comput. 10(4), 1898\u20131908 (2022)","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"key":"6_CR25","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2022.102801","volume":"135","author":"NN Sharma","year":"2023","unstructured":"Sharma, N.N., et al.: CLARINET: a quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. 135, 102801 (2023)","journal-title":"J. Syst. Archit."},{"key":"6_CR26","unstructured":"Lafage, V.: Revisiting what every computer scientist should know about floating-point arithmetic, arXiv preprint arXiv:2012.02492 (2020)"},{"key":"6_CR27","doi-asserted-by":"crossref","unstructured":"Cococcioni, M., Ruffaldi, E., Saponara, S.: Exploiting posit arithmetic for deep neural networks in autonomous driving applications. In: 2018 International Conference of Electrical and Electronic Technologies for Automotive, pp. 1\u20136. IEEE (2018)","DOI":"10.23919\/EETA.2018.8493233"},{"key":"6_CR28","unstructured":"Gustafson, J.L.: Posit arithmetic. Mathematica Notebook describing the posit number system, vol. 30 (2017)"}],"container-title":["Lecture Notes in Computer Science","Next Generation Arithmetic"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-32180-1_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,11]],"date-time":"2023-05-11T12:03:52Z","timestamp":1683806632000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-32180-1_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"ISBN":["9783031321795","9783031321801"],"references-count":28,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-32180-1_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]},"assertion":[{"value":"12 May 2023","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"CoNGA","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Conference on Next Generation Arithmetic","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Singapore","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Singapore","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2023","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"1 March 2023","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2 March 2023","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"4","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"conga2023","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/www.sc-asia.org\/conga\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Double-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easy Chair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"16","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"11","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"69% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}