{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T15:41:42Z","timestamp":1773157302358,"version":"3.50.1"},"publisher-location":"Cham","reference-count":25,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031416729","type":"print"},{"value":"9783031416736","type":"electronic"}],"license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023]]},"DOI":"10.1007\/978-3-031-41673-6_5","type":"book-chapter","created":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T16:03:31Z","timestamp":1692029011000},"page":"51-65","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Case Study for Running Memory-Bound Kernels on RISC-V CPUs"],"prefix":"10.1007","author":[{"given":"Valentin","family":"\u00a0Volokitin","sequence":"first","affiliation":[]},{"given":"Evgeny","family":"\u00a0Kozinov","sequence":"additional","affiliation":[]},{"given":"Valentina","family":"\u00a0Kustikova","sequence":"additional","affiliation":[]},{"given":"Alexey","family":"\u00a0Liniov","sequence":"additional","affiliation":[]},{"given":"Iosif","family":"\u00a0Meyerov","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,8,15]]},"reference":[{"key":"5_CR1","unstructured":"Asanovi\u0107, K., Patterson, D.A.: Instruction sets should be free: the case for RISC-V. EECS Department. University of California, Berkeley. UCB\/EECS-2014\u2013146 (2014)"},{"key":"5_CR2","unstructured":"Waterman, A., Asanovi\u0107, K.: The RISC-V instruction set manual, volume I: user-level ISA, document version 20190608-base-ratified. In: RISC-V Foundation (2019)"},{"key":"5_CR3","unstructured":"Furber, S.B.: VLSI RISC Architecture and Organization, 1st edn. CRC Press (1989)"},{"key":"5_CR4","unstructured":"Asanovi\u0107, K.: Advancing HPC with RISC-V. In: Invited Talk at Supercomputing Conference (2022)"},{"key":"5_CR5","unstructured":"McCalpin, J.: Memory bandwidth and machine balance in current high performance computers. IEEE Comput. TCCA Newsl., 19\u201324 (1995)"},{"key":"5_CR6","unstructured":"History \u2013 RISC-V International. https:\/\/riscv.org\/about\/history\/. Accessed 09 May 2023"},{"key":"5_CR7","unstructured":"Chen, T., Patterson, D.A.: RISC-V genealogy. EECS Department, University of California, Berkeley, Technical report UCB\/EECS-2016-6 (2016)"},{"key":"5_CR8","unstructured":"Waterman, A., Asanovic, K., Hauser, J.: The RISC-V instruction set manual, Volume II: privileged architecture, document version 20211203 (2021)"},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"Lee, Y., et al.: Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. In: 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1\u201345. IEEE (2015)","DOI":"10.1109\/HOTCHIPS.2015.7477469"},{"key":"5_CR10","doi-asserted-by":"crossref","unstructured":"Zimmer, B., et al.: A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. In: 2015 VLSI Circuits, pp. 316\u2013317. IEEE (2015)","DOI":"10.1109\/VLSIC.2015.7231305"},{"key":"5_CR11","doi-asserted-by":"crossref","unstructured":"Schmidt, C., et al.: Programmable fine-grained power management and system analysis of RISC-V vector processors in 28-nm FD-SOI. IEEE Solid State Circuits Lett. 3, 210\u2013213 (2020)","DOI":"10.1109\/LSSC.2020.3010295"},{"key":"5_CR12","doi-asserted-by":"crossref","unstructured":"Wright, J.C., et al.: A dual-core RISC-V vector processor with on-chip fine-grain power management in 28-nm FD-SOI. IEEE Trans. VLSI Syst. 28(12), 2721\u20132725 (2020)","DOI":"10.1109\/TVLSI.2020.3030243"},{"key":"5_CR13","doi-asserted-by":"crossref","unstructured":"Celio, C., et al.: BROOM: an open-source out-of-order processor with resilient low-voltage operation in 28-nm CMOS. IEEE Micro 39(2), 52\u201360 (2019)","DOI":"10.1109\/MM.2019.2897782"},{"key":"5_CR14","unstructured":"Zhao, J., et al.: SonicBOOM: the 3rd generation berkeley out-of-order machine. In: Fourth Workshop on Computer Architecture Research with RISC-V, vol. 5, pp. 1\u20137 (2020)"},{"key":"5_CR15","unstructured":"RISC-V BOOM. https:\/\/boom-core.org\/. Accessed 09 May 2023"},{"key":"5_CR16","unstructured":"BOOM: The Berkeley out-of-order RISC-V Processor. https:\/\/github.com\/riscv-boom. Accessed 09 May 2023"},{"key":"5_CR17","doi-asserted-by":"crossref","unstructured":"Bartolini, A., et al.: Monte cimone: paving the road for the first generation of RISC-V high-performance computers. In: 2022 IEEE 35th International System-on-Chip Conference (SOCC), pp. 1\u20136. IEEE (2022)","DOI":"10.1109\/SOCC56010.2022.9908096"},{"key":"5_CR18","unstructured":"Europe steps up as RISC-V ships 10bn cores. https:\/\/www.eenewseurope.com\/en\/europe-steps-up-as-risc-v-ships-10bn-cores\/. Accessed 09 May 2023"},{"key":"5_CR19","unstructured":"RISC-V Software Ecosystem Status. https:\/\/sites.google.com\/riscv.org\/software-ecosystem-status. Accessed 09 May 2023"},{"key":"5_CR20","unstructured":"Davis, J.D.: RISC-V in Europe: the road to an open source HPC stack. https:\/\/www.european-processor-initiative.eu\/wp-content\/uploads\/2022\/03\/EPI-@-HPC-User-Forum.pdf. Accessed 09 May 2023"},{"key":"5_CR21","unstructured":"First International workshop on RISC-V for HPC. https:\/\/riscv.epcc.ed.ac.uk\/community\/isc23-workshop\/. Accessed 09 May 2023"},{"key":"5_CR22","unstructured":"RISC-V ISA \u2013 MIPS. https:\/\/www.mips.com\/products\/risc-v\/. Accessed 09 May 2023"},{"key":"5_CR23","unstructured":"Framework Partnership Agreement for developing a large-scale European initiative for HPC ecosystem based on RISC-V. https:\/\/eurohpc-ju.europa.eu\/framework-partnership-agreement-fpa-developing-large-scale-european-initiative-high-performance_en. Accessed 09 May 2023"},{"key":"5_CR24","doi-asserted-by":"crossref","unstructured":"Chatterjee, S., Sen, S.: Cache-efficient matrix transposition. In: IEEE Proceedings Sixth International Symposium on High-Performance Computer Architecture, HPCA-6 (Cat. No. PR00550), pp. 195\u2013205 (2000)","DOI":"10.1109\/HPCA.2000.824350"},{"key":"5_CR25","doi-asserted-by":"crossref","unstructured":"Moradifar, M., Shahbahrami, A.: Performance improvement of Gaussian filter using SIMD technology. In: \u00a0International Conference on Machine Vision and Image Processing, pp. 1\u20136 (2020)","DOI":"10.1109\/MVIP49855.2020.9116883"}],"container-title":["Lecture Notes in Computer Science","Parallel Computing Technologies"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-41673-6_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,26]],"date-time":"2024-10-26T04:32:54Z","timestamp":1729917174000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-41673-6_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"ISBN":["9783031416729","9783031416736"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-41673-6_5","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]},"assertion":[{"value":"15 August 2023","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"PaCT","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Parallel Computing Technologies","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Astana","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Kazakhstan","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2023","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"21 August 2023","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"25 August 2023","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"17","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"pact2023","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/ssd.sscc.ru\/conference\/pact2023\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}