{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,28]],"date-time":"2025-03-28T05:58:19Z","timestamp":1743141499702,"version":"3.40.3"},"publisher-location":"Cham","reference-count":20,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031460760"},{"type":"electronic","value":"9783031460777"}],"license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023]]},"DOI":"10.1007\/978-3-031-46077-7_15","type":"book-chapter","created":{"date-parts":[[2023,11,6]],"date-time":"2023-11-06T11:01:58Z","timestamp":1699268518000},"page":"225-240","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["PATARA: Extension of\u00a0a\u00a0Verification Framework for\u00a0RISC-V Instruction Set Implementations"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3570-1638","authenticated-orcid":false,"given":"Sven","family":"Gesper","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8397-0069","authenticated-orcid":false,"given":"Fabian","family":"Stuckmann","sequence":"additional","affiliation":[]},{"given":"Lucy","family":"W\u00f6bbekind","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3503-8386","authenticated-orcid":false,"given":"Guillermo","family":"Pay\u00e1-Vay\u00e1","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2023,11,7]]},"reference":[{"key":"15_CR1","unstructured":"Ahmadi-Pour, S., Herdt, V., Drechsler, R.: Constrained random verification for RISC-V: overview, evaluation and discussion. In: MBMV 2021; 24th Workshop, pp. 1\u20138. VDE (2021)"},{"issue":"4","key":"15_CR2","doi-asserted-by":"publisher","first-page":"202","DOI":"10.1109\/LES.2021.3077368","volume":"13","author":"N Bruns","year":"2021","unstructured":"Bruns, N., Herdt, V., Gro\u00dfe, D., Drechsler, R.: Toward RISC-V CSR compliance testing. IEEE Embed. Syst. Lett. 13(4), 202\u2013205 (2021)","journal-title":"IEEE Embed. Syst. Lett."},{"key":"15_CR3","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1016\/j.scico.2015.10.012","volume":"118","author":"B Campbell","year":"2016","unstructured":"Campbell, B., Stark, I.: Randomised testing of a microprocessor model using SMT-solver state generation. Sci. Comput. Program. 118, 60\u201376 (2016)","journal-title":"Sci. Comput. Program."},{"key":"15_CR4","unstructured":"CHIPS Alliance: Random instruction generator for RISC-V processor verification. https:\/\/github.com\/google\/riscv-dv"},{"key":"15_CR5","doi-asserted-by":"crossref","unstructured":"Gautschi, M., et al.: Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices. IEEE Trans. Very Large Scale Int. (VLSI) Sys. 25(10), 2700\u20132713 (2017)","DOI":"10.1109\/TVLSI.2017.2654506"},{"issue":"1","key":"15_CR6","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/s11432-020-3308-4","volume":"65","author":"V Herdt","year":"2022","unstructured":"Herdt, V., Drechsler, R.: Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. 65(1), 1\u201317 (2022)","journal-title":"Sci. China Inf. Sci."},{"key":"15_CR7","doi-asserted-by":"crossref","unstructured":"Herdt, V., Gro\u00dfe, D., Drechsler, R.: Closing the RISC-V compliance gap: looking from the negative testing side. In: 2020 57th ACM\/IEEE Design Automation Conference (DAC), pp. 1\u20136. IEEE (2020)","DOI":"10.1109\/DAC18072.2020.9218629"},{"key":"15_CR8","doi-asserted-by":"crossref","unstructured":"Herdt, V., Gro\u00dfe, D., Drechsler, R.: Towards specification and testing of RISC-V ISA compliance. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 995\u2013998. IEEE (2020)","DOI":"10.23919\/DATE48585.2020.9116193"},{"key":"15_CR9","unstructured":"Imperas: Imperas delivers highest quality RISC-V RV32I compliance test suites to implementers and adopters of RISC-V. https:\/\/www.imperas.com\/articles\/imperas-delivers-highest-quality-risc-v-rv32i-compliance-test-suites-to-implementers-and"},{"key":"15_CR10","unstructured":"Imperas: Imperas RISC-V riscvOVPsim reference simulator and architectural validation tests (2022). https:\/\/www.ovpworld.org\/riscvOVPsimPlus"},{"key":"15_CR11","doi-asserted-by":"crossref","unstructured":"Josephson, D.: The good, the bad, and the ugly of silicon debug. In: Proceedings of the 43rd annual Design Automation Conference, pp. 3\u20136 (2006)","DOI":"10.1145\/1146909.1146915"},{"key":"15_CR12","doi-asserted-by":"crossref","unstructured":"Martignoni, L., Paleari, R., Roglia, G.F., Bruschi, D.: Testing CPU emulators. In: Proceedings of the 18th International Symposium on Software Testing And Analysis, pp. 261\u2013272 (2009)","DOI":"10.1145\/1572272.1572303"},{"key":"15_CR13","unstructured":"RISC-V: RISC-V Unit Tests (2020). https:\/\/github.com\/riscv\/riscv-tests"},{"key":"15_CR14","unstructured":"RISC-V Foundation: RISC-V Architecture Test SIG (2020). https:\/\/github.com\/riscv\/riscv-compliance. Accessed 20 Aug 2020"},{"key":"15_CR15","doi-asserted-by":"crossref","unstructured":"Schiavone, P.D., et al.: An open-source verification framework for open-source cores: A RISC-V case study. In: 2018 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 43\u201348. IEEE (2018)","DOI":"10.1109\/VLSI-SoC.2018.8644818"},{"key":"15_CR16","doi-asserted-by":"publisher","unstructured":"Stuckmann, F., Fistanto, P.A., Pay\u00e1-Vay\u00e1, G.: PATARA: a REVERSI-based open-source tool for post-silicon validation of processor cores. In: 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST), pp. 1\u20136 (2021). https:\/\/doi.org\/10.1109\/MOCAST52088.2021.9493373","DOI":"10.1109\/MOCAST52088.2021.9493373"},{"key":"15_CR17","doi-asserted-by":"publisher","unstructured":"Wagner, I., Bertacco, V.: REVERSI: post-silicon validation system for modern microprocessors. In: 2008 IEEE International Conference on Computer Design, pp. 307\u2013314. IEEE (2008). https:\/\/doi.org\/10.1109\/ICCD.2008.4751878","DOI":"10.1109\/ICCD.2008.4751878"},{"key":"15_CR18","unstructured":"Waterman, A., Asanovic, K.: The RISC-V Instruction Set Manual; Volume I: Unprivileged ISA (2019)"},{"key":"15_CR19","doi-asserted-by":"crossref","unstructured":"Waterman, A., Lee, Y., Patterson, D.A., Asanovi, K.: The RISC-V Instruction Set Manual. Volume 1: User-level IS, version 2.0. Technical report, California Univ. Berkeley Dept. of Electrical Engineering and Computer Sciences (2014)","DOI":"10.21236\/ADA605735"},{"key":"15_CR20","unstructured":"Waterman, A., Lee, Y., Patterson, D.A., Asanovic, K.: The RISC-V Instruction Set Manual, volume I: Base User-level ISA. EECS Department, UC Berkeley, Technical Report UCB\/EECS-2011-62 116 (2011)"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-46077-7_15","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,6]],"date-time":"2023-11-06T11:03:33Z","timestamp":1699268613000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-46077-7_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"ISBN":["9783031460760","9783031460777"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-46077-7_15","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2023]]},"assertion":[{"value":"7 November 2023","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SAMOS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Embedded Computer Systems","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Samos","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Greece","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2023","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2 July 2023","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"6 July 2023","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"23","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"samos2023","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/samos-conference.com\/wp\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Single-blind","order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Softconf","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"45","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"11","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"7","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"24% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"2","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Yes","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}