{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T12:20:17Z","timestamp":1742991617620,"version":"3.40.3"},"publisher-location":"Cham","reference-count":72,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031514784"},{"type":"electronic","value":"9783031514791"}],"license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024]]},"DOI":"10.1007\/978-3-031-51479-1_5","type":"book-chapter","created":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T07:02:33Z","timestamp":1704956553000},"page":"80-99","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Reviving Meltdown 3a"],"prefix":"10.1007","author":[{"given":"Daniel","family":"Weber","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabian","family":"Thomas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lukas","family":"Gerlach","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruiyi","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Schwarz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,1,12]]},"reference":[{"key":"5_CR1","unstructured":"Rogue system register read (2018). https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/rogue-system-register-read.html"},{"key":"5_CR2","doi-asserted-by":"crossref","unstructured":"Ac\u0131i\u00e7mez, O.: Yet another microarchitecutral attack: exploiting I-cache. In: ASPLOS (2007)","DOI":"10.1145\/1314466.1314469"},{"key":"5_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1007\/11967668_15","volume-title":"Topics in Cryptology \u2013 CT-RSA 2007","author":"O Ac\u0131i\u00e7mez","year":"2006","unstructured":"Ac\u0131i\u00e7mez, O., Ko\u00e7, \u00c7.K., Seifert, J.-P.: Predicting secret keys via branch prediction. In: Abe, M. (ed.) CT-RSA 2007. LNCS, vol. 4377, pp. 225\u2013242. Springer, Heidelberg (2006). https:\/\/doi.org\/10.1007\/11967668_15"},{"key":"5_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"256","DOI":"10.1007\/978-3-540-79263-5_16","volume-title":"Topics in Cryptology \u2013 CT-RSA 2008","author":"O Ac\u0131i\u00e7mez","year":"2008","unstructured":"Ac\u0131i\u00e7mez, O., Schindler, W.: A vulnerability in RSA implementations due to instruction cache analysis and its demonstration on OpenSSL. In: Malkin, T. (ed.) CT-RSA 2008. LNCS, vol. 4964, pp. 256\u2013273. Springer, Heidelberg (2008). https:\/\/doi.org\/10.1007\/978-3-540-79263-5_16"},{"key":"5_CR5","doi-asserted-by":"crossref","unstructured":"Aldaya, A.C., Brumley, B.B., ul Hassan, S., Garc\u00eda, C.P., Tuveri, N.: Port contention for fun and profit. In: S &P (2018)","DOI":"10.1109\/SP.2019.00066"},{"key":"5_CR6","unstructured":"ARM: Cache Speculation Side-channels, version 2.5 (2020)"},{"key":"5_CR7","unstructured":"Bhattacharya, S., Maurice, C., Bhasin, S., Mukhopadhyay, D.: Template attack on blinded scalar multiplication with asynchronous perf-ioctl calls. Cryptology ePrint Archive, Report 2017\/968 (2017)"},{"key":"5_CR8","doi-asserted-by":"crossref","unstructured":"Bhattacharya, S., Mukhopadhyay, D.: Who watches the watchmen?: Utilizing performance monitors for compromising keys of RSA on Intel platforms. Cryptology ePrint Archive, Report 2015\/621 (2015)","DOI":"10.1007\/978-3-662-48324-4_13"},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"Canella, C., Schwarz, M., Haubenwallner, M., Schwarzl, M., Gruss, D.: KASLR: break it, fix it, repeat. In: Asia CCS (2020)","DOI":"10.1145\/3320269.3384747"},{"key":"5_CR10","unstructured":"Canella, C., et al.: A systematic evaluation of transient execution attacks and defenses. In: USENIX Security Symposium (2019). Extended classification tree and PoCs at https:\/\/transient.fail\/"},{"key":"5_CR11","doi-asserted-by":"crossref","unstructured":"Chiappetta, M., Savas, E., Yilmaz, C.: Real time detection of cache-based side-channel attacks using hardware performance counters. ePrint 2015\/1034 (2015)","DOI":"10.1016\/j.asoc.2016.09.014"},{"key":"5_CR12","unstructured":"Dixon, L.: Breaking KASLR with perf (2017). https:\/\/blog.lizzie.io\/kaslr-and-perf.html"},{"key":"5_CR13","unstructured":"Frisk, U.: Windows 10 KASLR Recovery with TSX (2016). https:\/\/blog.frizk.net\/2016\/11\/windows-10-kaslr-recovery-with-tsx.html"},{"key":"5_CR14","unstructured":"Garc\u00eda, C.P., Ul Hassan, S., Tuveri, N., Gridin, I., Aldaya, A.C., Brumley, B.B.: Certified side channels. In: USENIX Security Symposium (2020)"},{"key":"5_CR15","doi-asserted-by":"crossref","unstructured":"Gerlach, L., Weber, D., Zhang, R., Schwarz, M.: A security RISC: microarchitectural attacks on hardware RISC-V CPUs. In: S &P (2023)","DOI":"10.1109\/SP46215.2023.10179399"},{"key":"5_CR16","doi-asserted-by":"crossref","unstructured":"Gras, B., Giuffrida, C., Kurth, M., Bos, H., Razavi, K.: ABSynthe: automatic blackbox side-channel synthesis on commodity microarchitectures. In: NDSS (2020)","DOI":"10.14722\/ndss.2020.23018"},{"key":"5_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1007\/978-3-319-62105-0_11","volume-title":"Engineering Secure Software and Systems","author":"D Gruss","year":"2017","unstructured":"Gruss, D., Lipp, M., Schwarz, M., Fellner, R., Maurice, C., Mangard, S.: KASLR is dead: long live KASLR. In: Bodden, E., Payer, M., Athanasopoulos, E. (eds.) ESSoS 2017. LNCS, vol. 10379, pp. 161\u2013176. Springer, Cham (2017). https:\/\/doi.org\/10.1007\/978-3-319-62105-0_11"},{"key":"5_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"279","DOI":"10.1007\/978-3-319-40667-1_14","volume-title":"Detection of Intrusions and Malware, and Vulnerability Assessment","author":"D Gruss","year":"2016","unstructured":"Gruss, D., Maurice, C., Wagner, K., Mangard, S.: Flush+Flush: a fast and stealthy cache attack. In: Caballero, J., Zurutuza, U., Rodr\u00edguez, R.J. (eds.) DIMVA 2016. LNCS, vol. 9721, pp. 279\u2013299. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-40667-1_14"},{"key":"5_CR19","unstructured":"Gruss, D., Spreitzer, R., Mangard, S.: Cache template attacks: automating attacks on inclusive last-level caches. In: USENIX Security Symposium (2015)"},{"key":"5_CR20","unstructured":"Herath, N., Fogh, A.: These are not your grand Daddys CPU performance counters - CPU hardware performance counters for security. In: Black Hat Briefings (2015)"},{"key":"5_CR21","doi-asserted-by":"publisher","first-page":"116","DOI":"10.1007\/978-3-031-09484-2_7","volume-title":"DIMVA 2022","author":"L Hetterich","year":"2022","unstructured":"Hetterich, L., Schwarz, M.: Branch different - spectre attacks on apple silicon. In: Cavallaro, L., Gruss, D., Pellegrino, G., Giacinto, G. (eds.) DIMVA 2022. LNCS, vol. 13358, pp. 116\u2013135. Springer, Cham (2022). https:\/\/doi.org\/10.1007\/978-3-031-09484-2_7"},{"key":"5_CR22","doi-asserted-by":"crossref","unstructured":"Huo, T., et al.: Bluethunder: a 2-level directional predictor based side-channel attack against SGX. In: CHES (2020)","DOI":"10.46586\/tches.v2020.i1.321-347"},{"key":"5_CR23","unstructured":"Intel: Instructions affected by rogue system register read (2018). https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/resources\/instructions-affected-rogue-system-register-read.html"},{"key":"5_CR24","unstructured":"Intel: Intel-SA-00115 Q2 2018 Speculative Execution Side Channel Update (2019). https:\/\/www.intel.com\/content\/www\/us\/en\/security-center\/advisory\/intel-sa-00115.html"},{"key":"5_CR25","unstructured":"Intel: Affected Processors: Transient Execution Attacks (2023). https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/topic-technology\/software-security-guidance\/processors-affected-consolidated-product-cpu-model.html"},{"key":"5_CR26","unstructured":"Intel Corporation: Guidelines for Mitigating Timing Side Channels Against Cryptographic Implementations (2020). https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/secure-coding\/mitigate-timing-side-channel-crypto-implementation.html"},{"key":"5_CR27","unstructured":"Intel Corporation: Refined Speculative Execution Terminology (2020). https:\/\/software.intel.com\/security-software-guidance\/insights\/refined-speculative-execution-terminology"},{"key":"5_CR28","doi-asserted-by":"crossref","unstructured":"Irazoqui, G., Eisenbarth, T., Sunar, B.: MASCAT: stopping microarchitectural attacks before execution. ePrint 2016\/1196 (2017)","DOI":"10.1145\/3176258.3176316"},{"key":"5_CR29","doi-asserted-by":"crossref","unstructured":"Irazoqui, G., Eisenbarth, T., Sunar, B.: MASCAT: preventing microarchitectural attacks before distribution. In: CODASPY (2018)","DOI":"10.1145\/3176258.3176316"},{"key":"5_CR30","doi-asserted-by":"crossref","unstructured":"Kocher, P., et al.: Spectre attacks: exploiting speculative execution. In: S &P (2019)","DOI":"10.1109\/SP.2019.00002"},{"key":"5_CR31","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"104","DOI":"10.1007\/3-540-68697-5_9","volume-title":"Advances in Cryptology \u2014 CRYPTO \u201996","author":"PC Kocher","year":"1996","unstructured":"Kocher, P.C.: Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104\u2013113. Springer, Heidelberg (1996). https:\/\/doi.org\/10.1007\/3-540-68697-5_9"},{"key":"5_CR32","unstructured":"Koruyeh, E.M., Khasawneh, K., Song, C., Abu-Ghazaleh, N.: Spectre returns! Speculation attacks using the return stack buffer. In: WOOT (2018)"},{"key":"5_CR33","unstructured":"Lee, S., Shih, M., Gera, P., Kim, T., Kim, H., Peinado, M.: Inferring fine-grained control flow inside SGX enclaves with branch shadowing. In: USENIX Security Symposium (2017)"},{"key":"5_CR34","unstructured":"Lipp, M., Gruss, D., Spreitzer, R., Maurice, C., Mangard, S.: ARMageddon: cache attacks on mobile devices. In: USENIX Security Symposium (2016)"},{"key":"5_CR35","doi-asserted-by":"crossref","unstructured":"Lipp, M., et al.: PLATYPUS: software-based power side-channel attacks on x86. In: S &P (2020)","DOI":"10.1109\/SP40001.2021.00063"},{"key":"5_CR36","unstructured":"Lipp, M., et al.: Meltdown: reading kernel memory from user space. In: USENIX Security Symposium (2018)"},{"key":"5_CR37","doi-asserted-by":"crossref","unstructured":"Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-level cache side-channel attacks are practical. In: S &P (2015)","DOI":"10.1109\/SP.2015.43"},{"key":"5_CR38","doi-asserted-by":"crossref","unstructured":"Lou, X., Zhang, T., Jiang, J., Zhang, Y.: A survey of microarchitectural side-channel vulnerabilities, attacks, and defenses in cryptography. In: ACM CSUR (2021)","DOI":"10.1145\/3456629"},{"key":"5_CR39","unstructured":"Lutas, A., Lutas, D.: Bypassing KPTI using the speculative behavior of the SWAPGS instruction. In: BlackHat Europe (2019)"},{"key":"5_CR40","doi-asserted-by":"crossref","unstructured":"Maisuradze, G., Rossow, C.: ret2spec: speculative execution using return stack buffers. In: CCS (2018)","DOI":"10.1145\/3243734.3243761"},{"key":"5_CR41","unstructured":"Moghimi, D., Lipp, M., Sunar, B., Schwarz, M.: Medusa: microarchitectural data leakage via automated attack synthesis. In: USENIX Security Symposium (2020)"},{"key":"5_CR42","doi-asserted-by":"crossref","unstructured":"Mushtaq, M., Akram, A., Bhatti, M.K., Chaudhry, M., Lapotre, V., Gogniat, G.: Nights-watch: a cache-based side-channel intrusion detector using hardware performance counters. In: HASP (2018)","DOI":"10.1145\/3214292.3214293"},{"key":"5_CR43","doi-asserted-by":"publisher","first-page":"83871","DOI":"10.1109\/ACCESS.2020.2988370","volume":"8","author":"M Mushtaq","year":"2020","unstructured":"Mushtaq, M., et al.: WHISPER: a tool for run-time detection of side-channel attacks. IEEE Access 8, 83871\u201383900 (2020)","journal-title":"IEEE Access"},{"key":"5_CR44","doi-asserted-by":"crossref","unstructured":"Oren, Y., Kemerlis, V.P., Sethumadhavan, S., Keromytis, A.D.: The spy in the sandbox: practical cache attacks in JavaScript and their implications. In: CCS (2015)","DOI":"10.1145\/2810103.2813708"},{"key":"5_CR45","unstructured":"Paccagnella, R., Luo, L., Fletcher, C.W.: Lord of the ring (s): side channel attacks on the CPU on-chip ring interconnect are practical. In: USENIX Security Symposium (2021)"},{"key":"5_CR46","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"138","DOI":"10.1007\/978-3-319-30806-7_9","volume-title":"Engineering Secure Software and Systems","author":"M Payer","year":"2016","unstructured":"Payer, M.: HexPADS: a platform to detect \u201cstealth\u2019\u2019 attacks. In: Caballero, J., Bodden, E., Athanasopoulos, E. (eds.) ESSoS 2016. LNCS, vol. 9639, pp. 138\u2013154. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-30806-7_9"},{"key":"5_CR47","unstructured":"Percival, C.: Cache missing for fun and profit. In: BSDCan (2005)"},{"key":"5_CR48","doi-asserted-by":"crossref","unstructured":"Purnal, A., Turan, F., Verbauwhede, I.: Prime+Scope: overcoming the observer effect for high-precision cache contention attacks. In: CCS (2021)","DOI":"10.1145\/3460120.3484816"},{"key":"5_CR49","unstructured":"Qiu, P., et al.: PMUSpill: the counters in performance monitor unit that leak SGX-protected secrets. arXiv:2207.11689 (2022)"},{"key":"5_CR50","unstructured":"Ragab, H., Barberis, E., Bos, H., Giuffrida, C.: Rage against the machine clear: a systematic analysis of machine clears and their implications for transient execution attacks. In: USENIX Security (2021)"},{"key":"5_CR51","doi-asserted-by":"crossref","unstructured":"Ragab, H., Milburn, A., Razavi, K., Bos, H., Giuffrida, C.: CrossTalk: speculative data leaks across cores are real. In: S &P (2021)","DOI":"10.1109\/SP40001.2021.00020"},{"key":"5_CR52","doi-asserted-by":"publisher","first-page":"209","DOI":"10.1007\/978-3-031-17143-7_11","volume-title":"Computer Security - ESORICS 2022","author":"T Rokicki","year":"2022","unstructured":"Rokicki, T., Maurice, C., Schwarz, M.: CPU port contention without SMT. In: Atluri, V., Di Pietro, R., Jensen, C.D., Meng, W. (eds.) ESORICS 2022. LNCS, vol. 13556, pp. 209\u2013228. Springer, Cham (2022). https:\/\/doi.org\/10.1007\/978-3-031-17143-7_11"},{"key":"5_CR53","unstructured":"Schwarz, M., Canella, C., Giner, L., Gruss, D.: Store-to-leak forwarding: leaking data on meltdown-resistant CPUs. arXiv:1905.05725 (2019)"},{"key":"5_CR54","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1007\/978-3-319-60876-1_1","volume-title":"Detection of Intrusions and Malware, and Vulnerability Assessment","author":"M Schwarz","year":"2017","unstructured":"Schwarz, M., Weiser, S., Gruss, D., Maurice, C., Mangard, S.: Malware guard extension: using SGX to conceal cache attacks. In: Polychronakis, M., Meier, M. (eds.) DIMVA 2017. LNCS, vol. 10327, pp. 3\u201324. Springer, Cham (2017). https:\/\/doi.org\/10.1007\/978-3-319-60876-1_1"},{"key":"5_CR55","doi-asserted-by":"crossref","unstructured":"Schwarz, M., et al.: KeyDrown: eliminating software-based keystroke timing side-channel attacks. In: NDSS (2018)","DOI":"10.14722\/ndss.2018.23027"},{"key":"5_CR56","doi-asserted-by":"crossref","unstructured":"Schwarz, M., et al.: ZombieLoad: cross-privilege-boundary data sampling. In: CCS (2019)","DOI":"10.1145\/3319535.3354252"},{"key":"5_CR57","doi-asserted-by":"crossref","unstructured":"Singh, B., Evtyushkin, D., Elwell, J., Riley, R., Cervesato, I.: On the detection of kernel-level rootkits using hardware performance counters. In: Asia CCS (2017)","DOI":"10.1145\/3052973.3052999"},{"key":"5_CR58","doi-asserted-by":"crossref","unstructured":"Uhsadel, L., Georges, A., Verbauwhede, I.: Exploiting hardware performance counters. In: 5th Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2008) (2008)","DOI":"10.1109\/FDTC.2008.19"},{"key":"5_CR59","unstructured":"Van Bulck, J., et al.: Foreshadow: extracting the keys to the Intel SGX kingdom with transient out-of-order execution. In: USENIX Security Symposium (2018)"},{"key":"5_CR60","doi-asserted-by":"crossref","unstructured":"Van Bulck, J., et al.: LVI: Hijacking transient execution through microarchitectural load value injection. In: S &P (2020)","DOI":"10.1109\/SP40000.2020.00089"},{"key":"5_CR61","doi-asserted-by":"crossref","unstructured":"van Schaik, S., et al.: RIDL: rogue in-flight data load. In: S &P (2019)","DOI":"10.1109\/SP.2019.00087"},{"key":"5_CR62","unstructured":"Varda, K.: Dynamic process isolation: research by cloudflare and TU Graz (2021). https:\/\/blog.cloudflare.com\/spectre-research-with-tu-graz\/"},{"key":"5_CR63","doi-asserted-by":"crossref","unstructured":"Wang, H., Sayadi, H., Sasan, A., Rafatirad, S., Homayoun, H.: Hybrid-shield: accurate and efficient cross-layer countermeasure for run-time detection and mitigation of cache-based side-channel attacks. In: ICCAD (2020)","DOI":"10.1145\/3400302.3418783"},{"key":"5_CR64","doi-asserted-by":"crossref","unstructured":"Wang, H., Sayadi, H., Sasan, A., Rafatirad, S., Mohsenin, T., Homayoun, H.: Comprehensive evaluation of machine learning countermeasures for detecting microarchitectural side-channel attacks. In: GLSVLSI (2020)","DOI":"10.1145\/3386263.3407586"},{"key":"5_CR65","unstructured":"Weisse, O., et al.: Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution (2018). https:\/\/foreshadowattack.eu\/foreshadow-NG.pdf"},{"key":"5_CR66","doi-asserted-by":"crossref","unstructured":"Xiao, Y., Li, M., Chen, S., Zhang, Y.: STACCO: differentially analyzing side-channel traces for detecting SSL\/TLS vulnerabilities in secure enclaves. In: CCS (2017)","DOI":"10.1145\/3133956.3134016"},{"key":"5_CR67","unstructured":"Yarom, Y., Falkner, K.: Flush+Reload: a high resolution, low noise, L3 cache side-channel attack. In: USENIX Security Symposium (2014)"},{"key":"5_CR68","doi-asserted-by":"publisher","first-page":"99","DOI":"10.1007\/s13389-017-0152-y","volume":"7","author":"Y Yarom","year":"2017","unstructured":"Yarom, Y., Genkin, D., Heninger, N.: CacheBleed: a timing attack on OpenSSL constant-time RSA. JCEN 7, 99\u2013112 (2017). https:\/\/doi.org\/10.1007\/s13389-017-0152-y","journal-title":"JCEN"},{"key":"5_CR69","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"118","DOI":"10.1007\/978-3-319-45719-2_6","volume-title":"Research in Attacks, Intrusions, and Defenses","author":"T Zhang","year":"2016","unstructured":"Zhang, T., Zhang, Y., Lee, R.B.: CloudRadar: a real-time side-channel attack detection system in clouds. In: Monrose, F., Dacier, M., Blanc, G., Garcia-Alfaro, J. (eds.) RAID 2016. LNCS, vol. 9854, pp. 118\u2013140. Springer, Cham (2016). https:\/\/doi.org\/10.1007\/978-3-319-45719-2_6"},{"key":"5_CR70","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Juels, A., Reiter, M.K., Ristenpart, T.: Cross-VM side channels and their use to extract private keys. In: CCS (2012)","DOI":"10.1145\/2382196.2382230"},{"key":"5_CR71","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Reiter, M.: D\u00fcppel: retrofitting commodity operating systems to mitigate cache side channels in the cloud. In: CCS (2013)","DOI":"10.1145\/2508859.2516741"},{"key":"5_CR72","doi-asserted-by":"crossref","unstructured":"Zhang, Z., et al.: See through walls: detecting malware in SGX enclaves with SGX-bouncer. In: Asia CCS (2021)","DOI":"10.1145\/3433210.3437531"}],"container-title":["Lecture Notes in Computer Science","Computer Security \u2013 ESORICS 2023"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-51479-1_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T07:03:53Z","timestamp":1704956633000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-51479-1_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"ISBN":["9783031514784","9783031514791"],"references-count":72,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-51479-1_5","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2024]]},"assertion":[{"value":"12 January 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ESORICS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Symposium on Research in Computer Security","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"The Hague","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"The Netherlands","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2023","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"25 September 2023","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"29 September 2023","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"28","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"esorics2023","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/esorics2023.org\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"order":1,"name":"type","label":"Type","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"Easychair","order":2,"name":"conference_management_system","label":"Conference Management System","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"478","order":3,"name":"number_of_submissions_sent_for_review","label":"Number of Submissions Sent for Review","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"93","order":4,"name":"number_of_full_papers_accepted","label":"Number of Full Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"0","order":5,"name":"number_of_short_papers_accepted","label":"Number of Short Papers Accepted","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"19% - The value is computed by the equation \"Number of Full Papers Accepted \/ Number of Submissions Sent for Review * 100\" and then rounded to a whole number.","order":6,"name":"acceptance_rate_of_full_papers","label":"Acceptance Rate of Full Papers","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"3-4","order":7,"name":"average_number_of_reviews_per_paper","label":"Average Number of Reviews per Paper","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"10","order":8,"name":"average_number_of_papers_per_reviewer","label":"Average Number of Papers per Reviewer","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}},{"value":"No","order":9,"name":"external_reviewers_involved","label":"External Reviewers Involved","group":{"name":"ConfEventPeerReviewInformation","label":"Peer Review Information (provided by the conference organizers)"}}]}}