{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T09:03:56Z","timestamp":1743066236976,"version":"3.40.3"},"publisher-location":"Cham","reference-count":22,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031628733"},{"type":"electronic","value":"9783031628740"}],"license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024]]},"DOI":"10.1007\/978-3-031-62874-0_6","type":"book-chapter","created":{"date-parts":[[2024,6,21]],"date-time":"2024-06-21T07:02:17Z","timestamp":1718953337000},"page":"68-79","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Scratchy: A Class of\u00a0Adaptable Architectures with\u00a0Software-Managed Communication for\u00a0Edge Streaming Applications"],"prefix":"10.1007","author":[{"given":"Joseph W.","family":"Faye","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7058-9162","authenticated-orcid":false,"given":"Naouel","family":"Haggui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florent","family":"Kermarrec","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8122-1192","authenticated-orcid":false,"given":"Kevin J. M.","family":"Martin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7719-1106","authenticated-orcid":false,"given":"Shuvra","family":"Bhattacharyya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0609-4592","authenticated-orcid":false,"given":"Jean-Fran\u00e7ois","family":"Nezan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1158-0915","authenticated-orcid":false,"given":"Maxime","family":"Pelcat","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,6,22]]},"reference":[{"key":"6_CR1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-005-3590-6","author":"S Amarasinghe","year":"2005","unstructured":"Amarasinghe, S., et al.: Language and compiler design for streaming applications. Int. J. Parallel Prog. (2005). https:\/\/doi.org\/10.1007\/s10766-005-3590-6","journal-title":"Int. J. Parallel Prog."},{"key":"6_CR2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2996616","author":"A Amid","year":"2020","unstructured":"Amid, A., et al.: Chipyard: integrated design, simulation, and implementation framework for custom SoCs. IEEE Micro (2020). https:\/\/doi.org\/10.1109\/MM.2020.2996616","journal-title":"IEEE Micro"},{"key":"6_CR3","unstructured":"Asanovi\u0107, K., et al.: The rocket chip generator. Technical report, EECS Department, University of California, Berkeley (2016)"},{"key":"6_CR4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2997706","author":"J Balkind","year":"2020","unstructured":"Balkind, J., et al.: Openpiton at 5: a nexus for open and agile hardware design. IEEE Micro (2020). https:\/\/doi.org\/10.1109\/MM.2020.2997706","journal-title":"IEEE Micro"},{"key":"6_CR5","doi-asserted-by":"publisher","DOI":"10.1145\/2980024.2872414","author":"J Balkind","year":"2016","unstructured":"Balkind, J., et al.: Openpiton: an open source manycore research framework. SIGARCH Comput. Archit. News (2016). https:\/\/doi.org\/10.1145\/2980024.2872414","journal-title":"SIGARCH Comput. Archit. News"},{"key":"6_CR6","doi-asserted-by":"publisher","unstructured":"Banakar, R., Steinke, S., Lee, B.S., Balakrishnan, M., Marwedel, P.: Scratchpad memory: a design alternative for cache on-chip memory in embedded systems. In: Proceedings of the Tenth International Symposium on Hardware\/Software Codesign. CODES 2002 (IEEE Cat. No. 02TH8627) (2002). https:\/\/doi.org\/10.1145\/774789.774805","DOI":"10.1145\/774789.774805"},{"key":"6_CR7","unstructured":"Ghasemi, A.: Notifying memories for dataflow applications on shared-memory parallel computer. Ph.D. thesis, Universit\u00e9 de Bretagne Sud (2022). https:\/\/tel.archives-ouvertes.fr\/tel-03704297v2"},{"key":"6_CR8","doi-asserted-by":"publisher","unstructured":"Ghasemi, A., Cataldo, R., Diguet, J.P., Martin, K.J.M.: On cache limits for dataflow applications and related efficient memory management strategies. In: Workshop on Design and Architectures for Signal and Image Processing (14th Edition). Association for Computing Machinery (2021). https:\/\/doi.org\/10.1145\/3441110.3441573","DOI":"10.1145\/3441110.3441573"},{"key":"6_CR9","doi-asserted-by":"publisher","DOI":"10.1145\/3282307","author":"JL Hennessy","year":"2019","unstructured":"Hennessy, J.L., Patterson, D.A.: A new golden age for computer architecture. Commun. ACM (2019). https:\/\/doi.org\/10.1145\/3282307","journal-title":"Commun. ACM"},{"key":"6_CR10","unstructured":"Kermarrec, F., Bourdeauducq, S., Lann, J.L., Badier, H.: Litex: an open-source SoC builder and library based on migen python DSL. CoRR (2020). https:\/\/api.semanticscholar.org\/CorpusID:199423893"},{"key":"6_CR11","unstructured":"Krishnasamy, E., Varrette, S., Mucciardi, M.: Edge computing: an overview of framework and applications. Technical report, PRACE aisbl, Bruxelles, Belgium (2020)"},{"key":"6_CR12","doi-asserted-by":"publisher","unstructured":"Kurth, A., Capotondi, A., Vogel, P., Benini, L., Marongiu, A.: HERO: an open-source research platform for HW\/SW exploration of heterogeneous manycore systems. In: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy Efficient HPC Systems. ACM (2018). https:\/\/doi.org\/10.1145\/3295816.3295821","DOI":"10.1145\/3295816.3295821"},{"key":"6_CR13","doi-asserted-by":"publisher","unstructured":"Liu, T., Tanougast, C., Weber, S.: Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system. In: 2006 13th IEEE International Conference on Electronics, Circuits and Systems, pp. 1085\u20131088 (2006). https:\/\/doi.org\/10.1109\/ICECS.2006.379627","DOI":"10.1109\/ICECS.2006.379627"},{"key":"6_CR14","doi-asserted-by":"publisher","unstructured":"Martin, K.J.M., Rizk, M., Sepulveda, M.J., Diguet, J.P.: Notifying memories: a case-study on data-flow applications with NoC interfaces implementation. In: Proceedings of the 53rd Annual Design Automation Conference. ACM, New York (2016). https:\/\/doi.org\/10.1145\/2897937.2898051","DOI":"10.1145\/2897937.2898051"},{"key":"6_CR15","doi-asserted-by":"publisher","unstructured":"Maurer, P.: The florida hardware design language. In: IEEE Proceedings on Southeastcon (1990). https:\/\/doi.org\/10.1109\/SECON.1990.117849","DOI":"10.1109\/SECON.1990.117849"},{"key":"6_CR16","doi-asserted-by":"publisher","DOI":"10.1109\/32.825767","author":"N Medvidovic","year":"2000","unstructured":"Medvidovic, N., Taylor, R.: A classification and comparison framework for software architecture description languages. IEEE Trans. Software Eng. (2000). https:\/\/doi.org\/10.1109\/32.825767","journal-title":"IEEE Trans. Software Eng."},{"key":"6_CR17","doi-asserted-by":"crossref","unstructured":"Mellor-Crummey, J.M., Scott, M.L.: Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. Comput. Syst. (1991)","DOI":"10.1145\/109625.109637"},{"key":"6_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1119","DOI":"10.1007\/978-3-540-30117-2_143","volume-title":"Field Programmable Logic and Application","author":"P Niang","year":"2004","unstructured":"Niang, P., Grandpierre, T., Akil, M., Sorel, Y.: AAA and SynDEx-Ic: a methodology and a software framework for the implementation of real-time applications onto reconfigurable circuits. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 1119\u20131123. Springer, Heidelberg (2004). https:\/\/doi.org\/10.1007\/978-3-540-30117-2_143"},{"key":"6_CR19","doi-asserted-by":"publisher","unstructured":"Pelcat, M., Desnos, K., Heulot, J., Guy, C., Nezan, J.F., Aridhi, S.: Preesm: a dataflow-based rapid prototyping framework for simplifying multicore DSP programming. In: 2014 6th European Embedded Design in Education and Research Conference (EDERC) (2014). https:\/\/doi.org\/10.1109\/EDERC.2014.6924354","DOI":"10.1109\/EDERC.2014.6924354"},{"key":"6_CR20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2996145","author":"D Petrisko","year":"2020","unstructured":"Petrisko, D., et al.: BlackParrot: an agile open-source RISC-V multicore for accelerator SoCs. IEEE Micro (2020). https:\/\/doi.org\/10.1109\/MM.2020.2996145","journal-title":"IEEE Micro"},{"key":"6_CR21","doi-asserted-by":"publisher","unstructured":"Rouxel, B., Skalistis, S., Derrien, S., Puaut, I.: Hiding communication delays in contention-free execution for SPM-based multi-core architectures. In: Euromicro Conference on Real-Time Systems (2019). https:\/\/doi.org\/10.4230\/LIPIcs.ECRTS.2019.25","DOI":"10.4230\/LIPIcs.ECRTS.2019.25"},{"key":"6_CR22","doi-asserted-by":"publisher","unstructured":"Zuckerman, J., Mantovani, P., Giri, D., Carloni, L.P.: Enabling heterogeneous, multicore SoC research with RISC-V and ESP. arXiv (2022). https:\/\/doi.org\/10.48550\/arXiv.2206.01901","DOI":"10.48550\/arXiv.2206.01901"}],"container-title":["Lecture Notes in Computer Science","Design and Architectures for Signal and Image Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-62874-0_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,21]],"date-time":"2024-06-21T07:03:00Z","timestamp":1718953380000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-62874-0_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"ISBN":["9783031628733","9783031628740"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-62874-0_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2024]]},"assertion":[{"value":"22 June 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DASIP","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Workshop on Design and Architecture for Signal and Image Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Munich","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2024","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"17 January 2024","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"19 January 2024","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"17","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"dasip2024","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}