{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T16:37:58Z","timestamp":1775839078151,"version":"3.50.1"},"publisher-location":"Cham","reference-count":13,"publisher":"Springer Nature Switzerland","isbn-type":[{"value":"9783031628733","type":"print"},{"value":"9783031628740","type":"electronic"}],"license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024]]},"DOI":"10.1007\/978-3-031-62874-0_8","type":"book-chapter","created":{"date-parts":[[2024,6,21]],"date-time":"2024-06-21T07:02:17Z","timestamp":1718953337000},"page":"96-109","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Improving the\u00a0Energy Efficiency of\u00a0CNN Inference on\u00a0FPGA Using Partial Reconfiguration"],"prefix":"10.1007","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8788-7059","authenticated-orcid":false,"given":"Zhuoer","family":"Li","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7492-6936","authenticated-orcid":false,"given":"S\u00e9bastien","family":"Bilavarn","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,6,22]]},"reference":[{"key":"8_CR1","doi-asserted-by":"publisher","unstructured":"Farhadi, M., Ghasemi, M., Yang, Y.: A novel design of adaptive and hierarchical convolutional neural networks using partial reconfiguration on FPGA. In: IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, USA, pp. 1-7 (2019). https:\/\/doi.org\/10.1109\/HPEC.2019.8916237.","DOI":"10.1109\/HPEC.2019.8916237."},{"key":"8_CR2","doi-asserted-by":"publisher","first-page":"95571","DOI":"10.1109\/ACCESS.2022.3204704","volume":"10","author":"E Youssef","year":"2022","unstructured":"Youssef, E., Elsimary, H.A., El-Moursy, M.A., Mostafa, H., Khattab, A.: Energy-efficient precision-scaled cnn implementation with dynamic partial reconfiguration. IEEE Access 10, 95571\u201395584 (2022). https:\/\/doi.org\/10.1109\/ACCESS.2022.3204704","journal-title":"IEEE Access"},{"key":"8_CR3","doi-asserted-by":"publisher","unstructured":"Youssef, E., Elsemary, H.A., El-Moursy, M.A., Khattab, A., Mostafa, H.: Energy Adaptive convolution neural network using dynamic partial reconfiguration. in: IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), vol. 2020, pp. 325\u2013328. Springfield, MA, USA (2020). https:\/\/doi.org\/10.1109\/MWSCAS48704.2020.9184640","DOI":"10.1109\/MWSCAS48704.2020.9184640"},{"key":"8_CR4","doi-asserted-by":"publisher","unstructured":"Irmak, H., Ziener, D., Alachiotis, N.: Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. In: 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 2021, pp. 306-311. https:\/\/doi.org\/10.1109\/FPL53798.2021.00061.","DOI":"10.1109\/FPL53798.2021.00061."},{"key":"8_CR5","doi-asserted-by":"publisher","unstructured":"Alberto de Albuquerque Silva, C., Andrey Ramalho Diniz, A., Duarte D\u00f3ria Neto, A., Alberto Nicolau de Oliveira, J.: Use of partial reconfiguration for the implementation and embedding of the artificial neural network (ANN) in FPGA. In: 4th International Conference on Pervasive and Embedded Computing and Communication System (2014). https:\/\/doi.org\/10.5220\/0004716301420150.","DOI":"10.5220\/0004716301420150."},{"key":"8_CR6","doi-asserted-by":"publisher","unstructured":"Venieris, S.I., Bouganis, C.S.: fpgaConvNet: a framework for mapping convolutional neural networks on FPGAs. In: IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Washington, DC, USA, vol. 2016, pp. 40\u201347 (2016). https:\/\/doi.org\/10.1109\/FCCM.2016.22","DOI":"10.1109\/FCCM.2016.22"},{"key":"8_CR7","doi-asserted-by":"publisher","unstructured":"Kastner, F., Janben, B., Kautz, F., Hubner, M., Corradi, G.: Hardware, software codesign for convolutional neural networks exploiting dynamic partial reconfiguration on PYNQ. In: IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Vancouver, BC, Canada, vol. 2018, pp. 154\u2013161 (2018). https:\/\/doi.org\/10.1109\/IPDPSW.2018.00031","DOI":"10.1109\/IPDPSW.2018.00031"},{"key":"8_CR8","doi-asserted-by":"publisher","unstructured":"Bonamy, R., et al.: Energy efficient mapping on manycore with dynamic and partial reconfiguration: application to a smart camera. Inter. J. Circuit Theory Appli. (2018). https:\/\/doi.org\/10.1002\/cta.2508","DOI":"10.1002\/cta.2508"},{"key":"8_CR9","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2016.1448","author":"R Bonamy","year":"2016","unstructured":"Bonamy, R., Bilavarn, S., Chillet, D., Sentieys, O.: Power modeling and exploration of dynamic and partially reconfigurable systems. J. Low Power Electr. (2016). https:\/\/doi.org\/10.1166\/jolpe.2016.1448","journal-title":"J. Low Power Electr."},{"key":"8_CR10","doi-asserted-by":"publisher","unstructured":"Bonamy, R., Pham, H.-M., Pillement, S., Chillet, D.: UPaRC-Ultra-fast power-aware reconfiguration controller. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, vol. 2012, pp. 1373\u20131378 (2012). https:\/\/doi.org\/10.1109\/DATE.2012.6176705","DOI":"10.1109\/DATE.2012.6176705"},{"key":"8_CR11","doi-asserted-by":"publisher","unstructured":"Duhem, F., Muller, F., Bonamy, R., Bilavarn, S.: Fortress: a flow for design space exploration of partially reconfigurable systems. Design Autom. Embedded Syst., 301-326 (2015). https:\/\/doi.org\/10.1007\/s10617-015-9160-2.","DOI":"10.1007\/s10617-015-9160-2."},{"key":"8_CR12","doi-asserted-by":"publisher","unstructured":"Sadek, A., et al.: Supporting utilities for heterogeneous embedded image processing platforms (STHEM): an overview. In: International Symposium on Applied Reconfigurable Computing (ARC) (2018). https:\/\/doi.org\/10.1007\/978-3-319-78890-6_59","DOI":"10.1007\/978-3-319-78890-6_59"},{"key":"8_CR13","doi-asserted-by":"publisher","unstructured":"Rongshi, D., Yongming, T.: Accelerator implementation of Lenet-5 convolution neural network based on FPGA with HLS. In: 2019 3rd International Conference on Circuits, System and Simulation (ICCSS), Nanjing, China, pp. 64-67 (2019). https:\/\/doi.org\/10.1109\/CIRSYSSIM.2019.8935599.","DOI":"10.1109\/CIRSYSSIM.2019.8935599."}],"container-title":["Lecture Notes in Computer Science","Design and Architectures for Signal and Image Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-62874-0_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,21]],"date-time":"2024-06-21T07:03:03Z","timestamp":1718953383000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-62874-0_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"ISBN":["9783031628733","9783031628740"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-62874-0_8","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024]]},"assertion":[{"value":"22 June 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"DASIP","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Workshop on Design and Architecture for Signal and Image Processing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Munich","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2024","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"17 January 2024","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"19 January 2024","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"17","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"dasip2024","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}