{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T14:09:13Z","timestamp":1742911753156,"version":"3.40.3"},"publisher-location":"Cham","reference-count":52,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031709029"},{"type":"electronic","value":"9783031709036"}],"license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024]]},"DOI":"10.1007\/978-3-031-70903-6_2","type":"book-chapter","created":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:04:30Z","timestamp":1725487470000},"page":"24-44","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["ReminISCence: Trusted Monitoring Against Privileged Preemption Side-Channel Attacks"],"prefix":"10.1007","author":[{"given":"Weijie","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yinqian","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weizhong","family":"Qiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deqing","family":"Zou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hai","family":"Jin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,9,5]]},"reference":[{"key":"2_CR1","doi-asserted-by":"crossref","unstructured":"Ajorpaz, S.M., Pokam, G., Koruyeh, E.M., Garza, E., Abu-Ghazaleh, N.B., Jim\u00e9nez, D.A.: Perspectron: detecting invariant footprints of microarchitectural attacks with perceptron. In: 53rd Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, 17\u201321 October 2020, pp. 1124\u20131137. IEEE (2020)","DOI":"10.1109\/MICRO50266.2020.00093"},{"key":"2_CR2","unstructured":"Andrew, W., Krste, A., John, H.: The risc-v instruction set manual volume ii: Privileged architecture (2021)"},{"key":"2_CR3","unstructured":"Arm Limited: Security technology: building a secure system using trustzone technology. http:\/\/infocenter.arm.com\/help\/topic\/com.arm.doc.prd29-genc-009492c\/PRD29-GENC009492C_trustzone_security_whitepaper.pdf. Accessed Nov 2023"},{"key":"2_CR4","unstructured":"avpatel: Opensbi. https:\/\/github.com\/riscv-software-src\/opensbi. Accessed Nov 2023"},{"key":"2_CR5","unstructured":"Bahmani, R., Brasser, F., Dessouky, G., Jauernig, P., Klimmek, M., Sadeghi, A., Stapf, E.: CURE: a security architecture with customizable and resilient enclaves. In: Bailey, M.D., Greenstadt, R. (eds.) 30th USENIX Security Symposium, USENIX Security 2021, 11\u201313 August 2021, pp. 1073\u20131090. USENIX Association (2021)"},{"key":"2_CR6","doi-asserted-by":"crossref","unstructured":"Barthe, G., Gr\u00e9goire, B., Laporte, V.: Secure compilation of side-channel countermeasures: the case of cryptographic \u201cconstant-time\". In: 31st IEEE Computer Security Foundations Symposium, CSF 2018, Oxford, United Kingdom, 9\u201312 July 2018, pp. 328\u2013343. IEEE Computer Society (2018)","DOI":"10.1109\/CSF.2018.00031"},{"key":"2_CR7","doi-asserted-by":"crossref","unstructured":"Borrello, P., D\u2019Elia, D.C., Querzoni, L., Giuffrida, C.: Constantine: automatic side-channel resistance using efficient control and data flow linearization. In: Kim, Y., Kim, J., Vigna, G., Shi, E. (eds.) CCS 2021: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, 15\u201319 November 2021, pp. 715\u2013733. ACM (2021)","DOI":"10.1145\/3460120.3484583"},{"key":"2_CR8","unstructured":"Brasser, F., M\u00fcller, U., Dmitrienko, A., Kostiainen, K., Capkun, S., Sadeghi, A.: Software grand exposure: SGX cache attacks are practical. In: Enck, W., Mulliner, C. (eds.) 11th USENIX Workshop on Offensive Technologies, WOOT 2017, Vancouver, BC, Canada, 14\u201315 August 2017. USENIX Association (2017)"},{"key":"2_CR9","unstructured":"Bulck, J.V., et al.: Foreshadow: extracting the keys to the intel SGX kingdom with transient out-of-order execution. In: Enck, W., Felt, A.P. (eds.) 27th USENIX Security Symposium, USENIX Security 2018, Baltimore, MD, USA, 15\u201317 August 2018, pp. 991\u20131008. USENIX Association (2018)"},{"key":"2_CR10","doi-asserted-by":"crossref","unstructured":"Bulck, J.V., et al.: LVI: hijacking transient execution through microarchitectural load value injection. In: 2020 IEEE Symposium on Security and Privacy, SP 2020, San Francisco, CA, USA, 18\u201321 May 2020, pp. 54\u201372. IEEE (2020)","DOI":"10.1109\/SP40000.2020.00089"},{"key":"2_CR11","unstructured":"Bulck, J.V., Piessens, F., Strackx, R.: SGX-step: a practical attack framework for precise enclave execution control. In: Proceedings of the 2nd Workshop on System Software for Trusted Execution, SysTEX@SOSP 2017, Shanghai, China, 28 October 2017. pp. 4:1\u20134:6. ACM (2017)"},{"key":"2_CR12","doi-asserted-by":"crossref","unstructured":"Bulck, J.V., Piessens, F., Strackx, R.: Nemesis: studying microarchitectural timing leaks in rudimentary CPU interrupt logic. In: Lie, D., Mannan, M., Backes, M., Wang, X. (eds.) Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, CCS 2018, Toronto, ON, Canada, 15\u201319 October 2018, pp. 178\u2013195. ACM (2018)","DOI":"10.1145\/3243734.3243822"},{"key":"2_CR13","doi-asserted-by":"crossref","unstructured":"Chen, S., Zhang, X., Reiter, M.K., Zhang, Y.: Detecting privileged side-channel attacks in shielded execution with d\u00e9j\u00e0 vu. In: Karri, R., Sinanoglu, O., Sadeghi, A., Yi, X. (eds.) Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security, AsiaCCS 2017, Abu Dhabi, United Arab Emirates, 2\u20136 April 2017, pp. 7\u201318. ACM (2017)","DOI":"10.1145\/3052973.3053007"},{"key":"2_CR14","unstructured":"Clark, M.: rv8 benchmark suite. https:\/\/github.com\/michaeljclark\/rv8-bench. Accessed Nov 2023"},{"key":"2_CR15","unstructured":"Costan, V., Lebedev, I.A., Devadas, S.: Sanctum: minimal hardware extensions for strong software isolation. In: Holz, T., Savage, S. (eds.) 25th USENIX Security Symposium, USENIX Security 16, Austin, TX, USA, 10\u201312 August 2016, pp. 857\u2013874. USENIX Association (2016)"},{"key":"2_CR16","doi-asserted-by":"crossref","unstructured":"Das, S., Werner, J., Antonakakis, M., Polychronakis, M., Monrose, F.: Sok: the challenges, pitfalls, and perils of using hardware performance counters for security. In: 2019 IEEE Symposium on Security and Privacy, SP 2019, San Francisco, CA, USA, 19\u201323 May 2019, pp. 20\u201338. IEEE (2019)","DOI":"10.1109\/SP.2019.00021"},{"key":"2_CR17","unstructured":"Domingos, J.M., Tom\u00e1s, P., Sousa, L.: Supporting RISC-V performance counters through performance analysis tools for linux (perf). CoRR arxiv:2112.11767 (2021)"},{"key":"2_CR18","unstructured":"Gal-On, S., Levy, M.: Exploring coremark a benchmark maximizing simplicity and efficacy. The Embedded Microprocessor Benchmark Consortium (2012)"},{"key":"2_CR19","doi-asserted-by":"crossref","unstructured":"Gerlach, L., Weber, D., Zhang, R., Schwarz, M.: A security RISC: microarchitectural attacks on hardware RISC-V cpus. In: 44th IEEE Symposium on Security and Privacy, SP 2023, San Francisco, CA, USA, 21\u201325 May 2023, pp. 2321\u20132338. IEEE (2023)","DOI":"10.1109\/SP46215.2023.10179399"},{"key":"2_CR20","unstructured":"Gras, B., Razavi, K., Bos, H., Giuffrida, C.: Translation leak-aside buffer: Defeating cache side-channel protections with $$\\{$$TLB$$\\}$$ attacks. In: 27th USENIX Security Symposium (USENIX Security 2018), pp. 955\u2013972 (2018)"},{"key":"2_CR21","doi-asserted-by":"crossref","unstructured":"Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: a free, commercially representative embedded benchmark suite. In: Proceedings of the fourth annual IEEE international workshop on workload characterization. WWC-4 (Cat. No. 01EX538), pp. 3\u201314. IEEE (2001)","DOI":"10.1109\/WWC.2001.990739"},{"key":"2_CR22","unstructured":"H\u00e4hnel, M., Cui, W., Peinado, M.: High-resolution side channels for untrusted operating systems. In: Silva, D.D., Ford, B. (eds.) 2017 USENIX Annual Technical Conference, USENIX ATC 2017, Santa Clara, CA, USA, 12\u201314 July 2017, pp. 299\u2013312. USENIX Association (2017)"},{"key":"2_CR23","unstructured":"Intel: Intel software guard extensions programming reference. https:\/\/software.intel.com\/sites\/default\/files\/managed\/48\/88\/329298-002.pdf. Accessed Nov 2023"},{"key":"2_CR24","unstructured":"Intel: Intel trust domain extensions module base architecture specification. https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/733575. Accessed Nov 2023"},{"key":"2_CR25","doi-asserted-by":"crossref","unstructured":"Khasawneh, K.N., Abu-Ghazaleh, N.B., Ponomarev, D., Yu, L.: RHMD: evasion-resilient hardware malware detectors. In: Hunter, H.C., Moreno, J., Emer, J.S., S\u00e1nchez, D. (eds.) Proceedings of the 50th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, 14\u201318 October 2017, pp. 315\u2013327. ACM (2017)","DOI":"10.1145\/3123939.3123972"},{"key":"2_CR26","unstructured":"Kleen, A., Strong, B.: Intel processor trace on linux. Tracing Summit (2015)"},{"key":"2_CR27","doi-asserted-by":"crossref","unstructured":"Kocher, P., et al.: Spectre attacks: exploiting speculative execution. In: 2019 IEEE Symposium on Security and Privacy, SP 2019, San Francisco, CA, USA, 19\u201323 May 2019, pp. 1\u201319. IEEE (2019)","DOI":"10.1109\/SP.2019.00002"},{"key":"2_CR28","doi-asserted-by":"crossref","unstructured":"Kou, Z., He, W., Sinha, S., Zhang, W.: Load-step: a precise trustzone execution control framework for exploring new side-channel attacks like flush+evict. In: 58th ACM\/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, 5\u20139 December 2021, pp. 979\u2013984. IEEE (2021)","DOI":"10.1109\/DAC18074.2021.9586226"},{"key":"2_CR29","doi-asserted-by":"crossref","unstructured":"Krahn, R., et al.: TEEMon: a continuous performance monitoring framework for tees. In: Silva, D.D., Kapitza, R. (eds.) Middleware 2020: 21st International Middleware Conference, Delft, The Netherlands, 7\u201311 December 2020, pp. 178\u2013192. ACM (2020)","DOI":"10.1145\/3423211.3425677"},{"key":"2_CR30","doi-asserted-by":"publisher","first-page":"164597","DOI":"10.1109\/ACCESS.2021.3134256","volume":"9","author":"A Le","year":"2021","unstructured":"Le, A., Hoang, T., Dao, B., Tsukamoto, A., Suzaki, K., Pham, C.: A real-time cache side-channel attack detection system on RISC-V out-of-order processor. IEEE Access 9, 164597\u2013164612 (2021)","journal-title":"IEEE Access"},{"key":"2_CR31","doi-asserted-by":"crossref","unstructured":"Lee, D., Kohlbrenner, D., Shinde, S., Asanovic, K., Song, D.: Keystone: an open framework for architecting trusted execution environments. In: Bilas, A., Magoutis, K., Markatos, E.P., Kostic, D., Seltzer, M.I. (eds.) EuroSys 2020: Fifteenth EuroSys Conference 2020, Heraklion, Greece, 27\u201330 April 2020, pp. 38:1\u201338:16. ACM (2020)","DOI":"10.1145\/3342195.3387532"},{"key":"2_CR32","doi-asserted-by":"crossref","unstructured":"Lee, Y., Lee, J., Heo, I., Hwang, D., Paek, Y.: Using coresight PTM to integrate CRA monitoring ips in an arm-based soc. ACM Trans. Design Autom. Electr. Syst. 22(3), 52:1\u201352:25 (2017)","DOI":"10.1145\/3035965"},{"issue":"6","key":"2_CR33","first-page":"1320","volume":"71","author":"C Li","year":"2022","unstructured":"Li, C., Gaudiot, J.: Detecting spectre attacks using hardware performance counters. IEEE Trans. Comput. 71(6), 1320\u20131331 (2022)","journal-title":"IEEE Trans. Comput."},{"key":"2_CR34","unstructured":"Lipp, M., et al.: Meltdown. arXiv preprint arXiv:1801.01207 (2018)"},{"key":"2_CR35","doi-asserted-by":"crossref","unstructured":"Liu, C., Harris, A., Maas, M., Hicks, M.W., Tiwari, M., Shi, E.: GhostRider: a hardware-software system for memory trace oblivious computation. In: \u00d6zturk, \u00d6., Ebcioglu, K., Dwarkadas, S. (eds.) Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2015, Istanbul, Turkey, 14\u201318 March 2015, pp. 87\u2013101. ACM (2015)","DOI":"10.1145\/2694344.2694385"},{"key":"2_CR36","doi-asserted-by":"crossref","unstructured":"Liu, F., Yarom, Y., Ge, Q., Heiser, G., Lee, R.B.: Last-level cache side-channel attacks are practical. In: 2015 IEEE Symposium on Security and Privacy, SP 2015, San Jose, CA, USA, 17\u201321 May 2015, pp. 605\u2013622. IEEE Computer Society (2015)","DOI":"10.1109\/SP.2015.43"},{"key":"2_CR37","unstructured":"luojia65: Rustsbi. https:\/\/github.com\/rustsbi\/rustsbi. Accessed Nov 2023"},{"key":"2_CR38","doi-asserted-by":"crossref","unstructured":"Mambretti, A., Neugschwandtner, M., Sorniotti, A., Kirda, E., Robertson, W.K., Kurmus, A.: Speculator: a tool to analyze speculative execution attacks and mitigations. In: Balenson, D. (ed.) Proceedings of the 35th Annual Computer Security Applications Conference, ACSAC 2019, San Juan, PR, USA, 09\u201313 December 2019, pp. 747\u2013761. ACM (2019)","DOI":"10.1145\/3359789.3359837"},{"key":"2_CR39","doi-asserted-by":"crossref","unstructured":"Martin, R., Demme, J., Sethumadhavan, S.: TimeWarp: rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks. In: 39th International Symposium on Computer Architecture (ISCA 2012), Portland, OR, USA, 9\u201313 June 2012, pp. 118\u2013129 (2012)","DOI":"10.1109\/ISCA.2012.6237011"},{"key":"2_CR40","doi-asserted-by":"crossref","unstructured":"Mushtaq, M., Akram, A., Bhatti, M.K., Chaudhry, M., Lapotre, V., Gogniat, G.: NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters. In: Szefer, J., Shi, W., Lee, R.B. (eds.) Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2018, Los Angeles, CA, USA, 02 June 2018, pp. 1:1\u20131:8. ACM (2018)","DOI":"10.1145\/3214292.3214293"},{"key":"2_CR41","unstructured":"Nordby, J., Cooke, M., Horvath, A.: emlearn: machine learning inference engine for microcontrollers and embedded devices (2019)"},{"key":"2_CR42","unstructured":"Rane, A., Lin, C., Tiwari, M.: Raccoon: closing digital side-channels through obfuscated execution. In: Jung, J., Holz, T. (eds.) 24th USENIX Security Symposium, USENIX Security 15, Washington, D.C., USA,x 12\u201314 June 2015, pp. 431\u2013446. USENIX Association (2015)"},{"key":"2_CR43","unstructured":"Saileshwar, G., Qureshi, M.K.: MIRAGE: mitigating conflict-based cache attacks with a practical fully-associative design. In: Bailey, M.D., Greenstadt, R. (eds.) 30th USENIX Security Symposium, USENIX Security 2021, 11\u201313 August 2021, pp. 1379\u20131396. USENIX Association (2021)"},{"key":"2_CR44","doi-asserted-by":"publisher","first-page":"133520","DOI":"10.1109\/ACCESS.2021.3112202","volume":"9","author":"K Suzaki","year":"2021","unstructured":"Suzaki, K., Nakajima, K., Oi, T., Tsukamoto, A.: TS-Perf: general performance measurement of trusted execution environment and rich execution environment on Intel SGX, Arm TrustZone, and RISC-V Keystone. IEEE Access 9, 133520\u2013133530 (2021)","journal-title":"IEEE Access"},{"key":"2_CR45","doi-asserted-by":"crossref","unstructured":"Tan, Q., Zeng, Z., Bu, K., Ren, K.: PhantomCache: obfuscating cache conflicts with localized randomization. In: 27th Annual Network and Distributed System Security Symposium, NDSS 2020, San Diego, California, USA, 23\u201326 February 2020. The Internet Society (2020)","DOI":"10.14722\/ndss.2020.24086"},{"key":"2_CR46","doi-asserted-by":"crossref","unstructured":"Wang, W., et al.: Leaky cauldron on the dark land: Understanding memory side-channel hazards in SGX. In: Thuraisingham, B., Evans, D., Malkin, T., Xu, D. (eds.) Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, CCS 2017, Dallas, TX, USA, 30 October\u201303 November 2017, pp. 2421\u20132434. ACM (2017)","DOI":"10.1145\/3133956.3134038"},{"key":"2_CR47","unstructured":"Werner, M., Unterluggauer, T., Giner, L., Schwarz, M., Gruss, D., Mangard, S.: ScatterCache: thwarting cache attacks via cache set randomization. In: 28th USENIX Security Symposium, USENIX Security 2019, Santa Clara, CA, USA, 14\u201316 August 2019. pp. 675\u2013692 (2019)"},{"issue":"1","key":"2_CR48","doi-asserted-by":"publisher","first-page":"180","DOI":"10.46586\/tches.v2024.i1.180-206","volume":"2024","author":"L Wilke","year":"2024","unstructured":"Wilke, L., Wichelmann, J., Rabich, A., Eisenbarth, T.: Sev-step a single-stepping framework for AMD-SEV. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(1), 180\u2013206 (2024)","journal-title":"IACR Trans. Cryptogr. Hardw. Embed. Syst."},{"key":"2_CR49","doi-asserted-by":"crossref","unstructured":"Xu, Y., Cui, W., Peinado, M.: Controlled-channel attacks: deterministic side channels for untrusted operating systems. In: 2015 IEEE Symposium on Security and Privacy, SP 2015, San Jose, CA, USA, 17\u201321 May 2015, pp. 640\u2013656. IEEE Computer Society (2015)","DOI":"10.1109\/SP.2015.45"},{"key":"2_CR50","unstructured":"Yarom, Y., Falkner, K.: FLUSH+RELOAD: a high resolution, low noise, L3 cache side-channel attack. In: Fu, K., Jung, J. (eds.) Proceedings of the 23rd USENIX Security Symposium, San Diego, CA, USA, 20\u201322 August 2014, pp. 719\u2013732. USENIX Association (2014)"},{"key":"2_CR51","doi-asserted-by":"crossref","unstructured":"Zhang, T., Zhang, Y., Lee, R.B.: CloudRadar: a real-time side-channel attack detection system in clouds. In: Research in Attacks, Intrusions, and Defenses - 19th International Symposium, RAID 2016, Paris, France, 19\u201321 September 2016, Proceedings, pp. 118\u2013140 (2016)","DOI":"10.1007\/978-3-319-45719-2_6"},{"key":"2_CR52","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Juels, A., Reiter, M.K., Ristenpart, T.: Cross-vm side channels and their use to extract private keys. In: Yu, T., Danezis, G., Gligor, V.D. (eds.) the ACM Conference on Computer and Communications Security, CCS 2012, Raleigh, NC, USA, 16\u201318 October 2012, pp. 305\u2013316. ACM (2012)","DOI":"10.1145\/2382196.2382230"}],"container-title":["Lecture Notes in Computer Science","Computer Security \u2013 ESORICS 2024"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-70903-6_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T19:49:15Z","timestamp":1732736955000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-70903-6_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"ISBN":["9783031709029","9783031709036"],"references-count":52,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-70903-6_2","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2024]]},"assertion":[{"value":"5 September 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ESORICS","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"European Symposium on Research in Computer Security","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Bydgoszcz","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Poland","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2024","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16 September 2024","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"20 September 2024","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"29","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"esorics2024","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"https:\/\/esorics2024.org","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}