{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,15]],"date-time":"2025-06-15T04:01:32Z","timestamp":1749960092453,"version":"3.41.0"},"publisher-location":"Cham","reference-count":21,"publisher":"Springer Nature Switzerland","isbn-type":[{"type":"print","value":"9783031737152"},{"type":"electronic","value":"9783031737169"}],"license":[{"start":{"date-parts":[[2024,12,14]],"date-time":"2024-12-14T00:00:00Z","timestamp":1734134400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,12,14]],"date-time":"2024-12-14T00:00:00Z","timestamp":1734134400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025]]},"DOI":"10.1007\/978-3-031-73716-9_24","type":"book-chapter","created":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T06:17:35Z","timestamp":1734070655000},"page":"339-353","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Integrating RISC-V SIMT and Scalar Cores: Loosely to Tightly Coupled"],"prefix":"10.1007","author":[{"given":"Sooraj","family":"Chetput","sequence":"first","affiliation":[]},{"given":"Anusuya","family":"Nallathambi","sequence":"additional","affiliation":[]},{"given":"Spencer","family":"Bowles","sequence":"additional","affiliation":[]},{"given":"Justin","family":"Cambridge","sequence":"additional","affiliation":[]},{"given":"Alex","family":"Chitsazzadeh","sequence":"additional","affiliation":[]},{"given":"Gagan","family":"Gundala","sequence":"additional","affiliation":[]},{"given":"Zengxiang","family":"Han","sequence":"additional","affiliation":[]},{"given":"Johnathan","family":"Hong","sequence":"additional","affiliation":[]},{"given":"Guilliame","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Ronit","family":"Nallagatla","sequence":"additional","affiliation":[]},{"given":"Ansh","family":"Patel","sequence":"additional","affiliation":[]},{"given":"Khoi","family":"Pham","sequence":"additional","affiliation":[]},{"given":"Abinands","family":"Ramshanker","sequence":"additional","affiliation":[]},{"given":"Htet","family":"Yan","sequence":"additional","affiliation":[]},{"given":"FangLing","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Zach","family":"Lagpacan","sequence":"additional","affiliation":[]},{"given":"Clay","family":"Hughes","sequence":"additional","affiliation":[]},{"given":"Kevin","family":"Pedretti","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Johnson","sequence":"additional","affiliation":[]},{"given":"Timothy G.","family":"Rogers","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,12,14]]},"reference":[{"key":"24_CR1","unstructured":"Elsabbagh, F., Asgari, B., Kim, H., Yalamanchili, S.: Vortex RISC-V GPGPU System: Extending the ISA, Synthesizing the Microarchitecture, and Modeling the Software Stack. CARRV (2019)"},{"key":"24_CR2","unstructured":"Blaise, T., et al.: Vortex: An Open Source Reconfigurable RISC-V GPGPU Accelerator for Architecture Research. Hot Chips 32 (2020)"},{"key":"24_CR3","doi-asserted-by":"publisher","unstructured":"Tine, B., Yalamarthy, K.P., Elsabbagh, F., Hyesoon, K.: Vortex: extending the RISC-v isa for GPGPU and 3D-Graphics. In: MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture (2021). https:\/\/doi.org\/10.1145\/3466752.3480128","DOI":"10.1145\/3466752.3480128"},{"key":"24_CR4","doi-asserted-by":"publisher","unstructured":"Fung, W.W.L., Sham, I., Yuan, G., Aamodt, T.M.: Dynamic warp formation and scheduling for efficient GPU control flow. In: 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 2007) (2007). https:\/\/doi.org\/10.1109\/micro.2007.30","DOI":"10.1109\/micro.2007.30"},{"key":"24_CR5","doi-asserted-by":"publisher","unstructured":"Rhu, M., Erez, M.: The dual-path execution model for efficient GPU control flow. In: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2013). https:\/\/doi.org\/10.1109\/hpca.2013.6522352","DOI":"10.1109\/hpca.2013.6522352"},{"key":"24_CR6","unstructured":"White Paper | AMD GRAPHICS CORES NEXT (GCN) ARCHITECTURE (2012)"},{"key":"24_CR7","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1109\/mcse.2015.4","volume":"17","author":"JS Vetter","year":"2015","unstructured":"Vetter, J.S., Mittal, S.: Opportunities for nonvolatile memory systems in extreme-scale high-performance computing. Comput. Sci. Eng. 17, 73\u201382 (2015). https:\/\/doi.org\/10.1109\/mcse.2015.4","journal-title":"Comput. Sci. Eng."},{"key":"24_CR8","doi-asserted-by":"publisher","unstructured":"Luk, C.-K., Hong, S., Kim, H.: Qilin: exploitng parallelism on heterogeneous multiprocessors with adaptive mapping. In: Proceedings of the 42nd Annual IEEE\/ACM International Symposium on Microarchitecture (2009). https:\/\/doi.org\/10.1145\/1669112.1669121","DOI":"10.1145\/1669112.1669121"},{"key":"24_CR9","doi-asserted-by":"publisher","first-page":"953","DOI":"10.1016\/j.jpdc.2012.02.006","volume":"73","author":"A Nere","year":"2013","unstructured":"Nere, A., Franey, S., Hashmi, A., Lipasti, M.: Simulating cortical networks on heterogeneous multi-GPU systems. J. Parallel Distrib. Comput. 73, 953\u2013971 (2013). https:\/\/doi.org\/10.1016\/j.jpdc.2012.02.006","journal-title":"J. Parallel Distrib. Comput."},{"key":"24_CR10","doi-asserted-by":"publisher","DOI":"10.1145\/2482767.2482785","author":"J Shen","year":"2013","unstructured":"Shen, J., Varbanescu, A.L., Sips, H., et al.: Glinda: A frame work for accelerating imbalanced applications on heterogeneous platforms. Proc. ACM Int. Conf. Comput. Front. (2013). https:\/\/doi.org\/10.1145\/2482767.2482785","journal-title":"Proc. ACM Int. Conf. Comput. Front."},{"key":"24_CR11","doi-asserted-by":"publisher","unstructured":"Ding, S., He, J., Yan, H., Suel, T.: Using graphics processors for high performance IR query processing. In: Proceedings of the 18th International Conference on World Wide Web (2009). https:\/\/doi.org\/10.1145\/1526709.1526766","DOI":"10.1145\/1526709.1526766"},{"key":"24_CR12","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3173548","volume":"11","author":"MA Kadi","year":"2018","unstructured":"Kadi, M.A., Janssen, B., Yudi, J., Huebner, M.: General-purpose computing with soft GPUS on FPGAS. ACM Trans. Reconf. Technol. Syst. 11, 1\u201322 (2018). https:\/\/doi.org\/10.1145\/3173548","journal-title":"ACM Trans. Reconf. Technol. Syst."},{"key":"24_CR13","doi-asserted-by":"publisher","unstructured":"Balasubramanian, R., Gangadhar, V., Guo, Z., et al.: Miaow - an open source RTL implementation of a GPGPU. In: 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII) (2015). https:\/\/doi.org\/10.1109\/coolchips.2015.7158663","DOI":"10.1109\/coolchips.2015.7158663"},{"key":"24_CR14","doi-asserted-by":"crossref","unstructured":"Covey, J., Johnson, M.C.: System-on-a-chip design as a platform for teaching design and design flow integration. In: Proceedings of the 2019 on Great Lakes Symposium on VLSI, Tysons Corner, VA (2019)","DOI":"10.1145\/3299874.3318000"},{"key":"24_CR15","unstructured":"Stevens, J.R., Skubic, J., Colter, E., Swabey, M.: Purdue microbrewer: a microcontroller generator. In: RISCV Microelectronics Conference 2017 (2017)"},{"key":"24_CR16","unstructured":"Skubic, J., Stevens, J.R., Tan, C.Y., Johnson, M., Swabey, M.: RISCV-business: a configurable, extensible RISC-V core. In: RISCV Microelectronics Conference 2017 (2017)"},{"key":"24_CR17","doi-asserted-by":"crossref","unstructured":"Swabey, M.A., Johnson, M.C.: Satisfying ABET criterion using an industrial microelectronic skills incubator. In: 2015 IEEE International Conference on Microelectronics Systems Education (2015)","DOI":"10.1109\/MSE.2015.7160010"},{"key":"24_CR18","unstructured":"https:\/\/engineering.purdue.edu\/SoC-Team#chips"},{"key":"24_CR19","doi-asserted-by":"publisher","unstructured":"Waterman, A., Lee, Y., Patterson, D.A., Asanovi, K.: The RISC-V Instruction Set Manual Volume 1: User-Level ISA, Version 20 (2014). https:\/\/doi.org\/10.21236\/ada605735","DOI":"10.21236\/ada605735"},{"key":"24_CR20","doi-asserted-by":"publisher","unstructured":"Rhu, M., Erez, M.: The dual-path execution model for efficient GPU control flow. In: 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2013). https:\/\/doi.org\/10.1109\/hpca.2013.6522352","DOI":"10.1109\/hpca.2013.6522352"},{"key":"24_CR21","unstructured":"NVIDIA: PTX: Parallel Thread Execution ISA version 2.3 (2010).http:\/\/developer.nvidia.com\/compute\/cuda"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing. ISC High Performance 2024 International Workshops"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-031-73716-9_24","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,14]],"date-time":"2025-06-14T05:19:47Z","timestamp":1749878387000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-031-73716-9_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,14]]},"ISBN":["9783031737152","9783031737169"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-031-73716-9_24","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2024,12,14]]},"assertion":[{"value":"14 December 2024","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"ISC High Performance","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on High Performance Computing","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Hamburg","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Germany","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2023","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"12 May 2023","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"16 June 2023","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"supercomputing2023a","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}